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Rambus designed the countermeasures to protect Nvidia’s GPUs from side-channel attacks that steal encryption keys by measuring a device’s power consumption. Attacks like this can be used to break into protected systems, assist law enforcement…
Ed Sperling of Semiconductor Engineering observes that chipmakers are increasingly relying on architectural and micro-architectural changes as the “best hope” for optimizing power and performance across markets, process nodes and price points. “While discussion about the death of Moore’s Law predates the 1-micron process node, there is no question that it is getting harder for even […]
Esthela Gallardo and Patricia J. Teller have penned an article for HPC Wire that explores the various challenges associated with cross-accelerator performance profiling. As Gallardo and Teller note, high performance computing (HPC) systems are comprised of multiple compute nodes interconnected by a network. “Previously these nodes were composed solely of multi-core processors, but nowadays they also […]
Jeff Dorsch of Semiconductor Engineering recently noted that there are a number of distinct advantages and drawbacks to various compute engines available on the market today. “[For example], CPUs offer high capacity at low latency. GPUs have the highest per-pin bandwidth. And FPGAs are designed to be very general,” writes Dorsch. “But each also has […]
Jeff Dorsch of Semiconductor Engineering recently noted that there are a number of distinct advantages and drawbacks to various compute engines available on the market today. “[For example], CPUs offer high capacity at low latency. GPUs have the highest per-pin bandwidth. And FPGAs are designed to be very general,” writes Dorsch. “But each also has […]
CT-RSA 2017 RSA Conference Cryptographers’ Track San Francisco, February 14-17, 2017 Held in conjunction with RSA Conference USA CT-RSA 2017 Accepted Papers Call for Papers Original research papers pertaining to all aspects of cryptography are solicited. Topics include but are not limited to: Public-key algorithms Symmetric-key algorithms Hash functions and MAC algorithms Random Number Generators […]
The Atari 2600 (or VCS) – which hit the nascent video game market back in 1977 – packed 128 bytes RAM and an 8-bit MOS 6507 CPU clocked at a mere 1.19 MHz. According to Wikipedia, the RAM was tasked with handling run-time data, which included the call stack and the state of the game […]
A recent KitGuru report suggests AMD has designed its upcoming Radeon R9 380X with high bandwidth memory, or HBM, a next-gen stacked DRAM memory standard. Read first our primer on: HBM2E Implementation & Selection – The Ultimate Guide » “Although HBM provides DDR3 – like bit rate per pin (HBM1=1GHz, HBM2=2GHz), the standard more than […]
Northwest Logic’s MRAM Controller Core is validated with Everspin’s EMD3D064M, expanding the ST-MRAM ecosystem to enable low latency and high reliability storage systems Beaverton, OR – Feb 9, 2015 – Northwest Logic, a leading high-performance IP provider, and Everspin Technologies, Inc., the world’s leading developer and manufacturer of discrete and embedded Magnetic RAM “MRAM”, announces […]