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Found 87 Results
Accelerating high performance computing systems
https://www.rambus.com/blogs/accelerating-high-performance-computing-systems-2/Esthela Gallardo and Patricia J. Teller have penned an article for HPC Wire that explores the various challenges associated with cross-accelerator performance profiling. As Gallardo and Teller note, high performance computing (HPC) systems are comprised of multiple compute nodes interconnected by a network. “Previously these nodes were composed solely of multi-core processors, but nowadays they also […]
The growing demand for FPGAs in servers and data centers
http://www.rambusblog.com/2016/07/25/the-growing-demand-for-fpgas-in-servers-and-data-centers/#new_tabJeff Dorsch of Semiconductor Engineering recently noted that there are a number of distinct advantages and drawbacks to various compute engines available on the market today. “[For example], CPUs offer high capacity at low latency. GPUs have the highest per-pin bandwidth. And FPGAs are designed to be very general,” writes Dorsch. “But each also has […]
The growing demand for FPGAs in servers and data centers
https://www.rambus.com/blogs/the-growing-demand-for-fpgas-in-servers-and-data-centers-2/Jeff Dorsch of Semiconductor Engineering recently noted that there are a number of distinct advantages and drawbacks to various compute engines available on the market today. “[For example], CPUs offer high capacity at low latency. GPUs have the highest per-pin bandwidth. And FPGAs are designed to be very general,” writes Dorsch. “But each also has […]
CT-RSA 2017
https://www.rambus.com/ct-rsa-2017/CT-RSA 2017 RSA Conference Cryptographers’ Track San Francisco, February 14-17, 2017 Held in conjunction with RSA Conference USA CT-RSA 2017 Accepted Papers Call for Papers Original research papers pertaining to all aspects of cryptography are solicited. Topics include but are not limited to: Public-key algorithms Symmetric-key algorithms Hash functions and MAC algorithms Random Number Generators […]
From consoles to VR
https://www.rambus.com/blogs/from-consoles-to-vr-2/The Atari 2600 (or VCS) – which hit the nascent video game market back in 1977 – packed 128 bytes RAM and an 8-bit MOS 6507 CPU clocked at a mere 1.19 MHz. According to Wikipedia, the RAM was tasked with handling run-time data, which included the call stack and the state of the game […]
From GDDR to HBM
https://www.rambus.com/blogs/from-gddr-to-hbm-2/A recent KitGuru report suggests AMD has designed its upcoming Radeon R9 380X with high bandwidth memory, or HBM, a next-gen stacked DRAM memory standard. Read first our primer on: HBM2E Implementation & Selection – The Ultimate Guide » “Although HBM provides DDR3 – like bit rate per pin (HBM1=1GHz, HBM2=2GHz), the standard more than […]
Northwest Logic Offers MRAM Controller IP compatible with Everspin’s ST-MRAM
https://www.rambus.com/northwest-logic-offers-mram-controller-ip-compatible-everspins-st-mram/Northwest Logic’s MRAM Controller Core is validated with Everspin’s EMD3D064M, expanding the ST-MRAM ecosystem to enable low latency and high reliability storage systems Beaverton, OR – Feb 9, 2015 – Northwest Logic, a leading high-performance IP provider, and Everspin Technologies, Inc., the world’s leading developer and manufacturer of discrete and embedded Magnetic RAM “MRAM”, announces […]
