Found 154 Results

Accelerating AI/ML applications in the data center with HBM3

Semiconductor Engineering Editor in Chief Ed Sperling recently spoke with Frank Ferro, Senior Director of Product Management at Rambus, about accelerating AI/ML applications in the data center with HBM3. Introduced by JEDEC in early 2022, the latest iteration of the high bandwidth memory standard increases the per-pin data rate to 6.4 Gigabits per second (Gb/s), […]

DDR5 vs DDR4 DRAM – All the Advantages & Design Challenges

Last updated on: September 7, 2022 On July 14th, 2021, JEDEC announced the publication of the JESD79-5 DDR5 SDRAM standard signaling the industry transition to DDR5 server and client dual-inline memory modules (DIMMs). DDR5 memory brings a number of key performance gains to the table, as well as new design challenges. Computing system architects, designers, and […]

Rambus at DesignCon

Rambus @ DesignCon 2022 Join us at DesignCon for a full-day training session on Wednesday, April 6th! Our sessions will cover the future of data centers and evolution of memory systems, 2.5D/3.D architecture solutions, automotive security, as well as IP solutions including CXL, HBM3, GDDR6, and PCIe 6.0 interfaces. All sessions will be in Great […]

AI Accelerates HBM Momentum

In a recent EE Times article, Gary Hilson notes that high bandwidth memory (HBM) deployments are becoming more mainstream due to the massive growth and diversity in artificial intelligence (AI) applications. “HBM is [now] less than niche. It’s even become less expensive, but it’s still a premium memory and requires expertise to implement,” writes Hilson. […]

How Rambus is Making Data Faster and Safer in 2022 and Beyond

Throughout 2021 and early 2022, Rambus has continued to make data faster and safer with the launch of key products, industry initiatives, and strategic partnerships. To address the insatiable demand for more bandwidth in the data center, we announced our 8.4 Gbps HBM3-Ready Memory Subsystem, confirmed the sampling of our DDR5 5600 MT/s 2nd-generation RCD chip, demonstrated our PCI Express® (PCIe) 5.0 digital controller IP on leading FPGA platforms, and unveiled our CXL Memory Interconnect Initiative. Looking ahead to 2022 and beyond, these products, initiatives, and partnerships will help power the […]

PCIE 6.0 – All you need to know about PCI Express Gen6

While the PCI-SIG has announced that the release of the PCI Express® 6.0 (PCIe 6.0) specification should arrive in 2022, Rambus is already addressing the needs of early adopters looking for the most advanced PCIe 6.0 IP solutions for their SoC and ASIC designs. You can find all about the new generation specification in the article below. Contents What is PCIe 6.0? What’s new with PCIe 6.0? Why PCIe 6.0 now? […]

Compute Express Link (CXL): All you need to know

In this blog post, we take an in-depth look at Compute Express Link ™ (CXL) 2.0, an open standard cache-coherent interconnect between processors and accelerators, smart NICs, and memory devices. We explore how CXL is helping data centers more efficiently handle the yottabytes of data generated by artificial intelligence (AI) and machine learning (ML) applications. […]

Hardware Root of Trust: Everything you need to know

Last updated on: October 29, 2021 As explained in our “Secure Silicon IP Webinar Series“, a root of trust is the security foundation for an SoC, other semiconductor device or electronic system. However, its meaning differs depending on who you ask. For example, the hardware root of trust contains the keys for cryptographic functions and […]

Side-channel attacks explained: everything you need to know

In this blog post, we take an in-depth look at the world of side-channel attacks. We describe how side-channel attacks work and detail some of the most common attack methodologies. We also explore differential power analysis (DPA), an extremely powerful side-channel attack capable of obtaining and analyzing statistical measurements across multiple operations. In addition, we […]

CXL 2.0 Controller

Interface IP CXL 2.0 Controller Rambus Compute Express Link (CXL) 2.0 Controller (formerly XpressLINK) leverages a silicon-proven PCIe 5.0 controller architecture for the path, and adds CXL.cache and CXL.mem paths specific to the CXL standard. The controller exposes a native Tx/Rx user interface for traffic as well as an Intel CXL-cache/mem Protocol Interface […]