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In this blog post, we take an in-depth look at the world of side-channel attacks. We describe how side-channel attacks work and detail some of the most common attack methodologies. We also explore differential power analysis (DPA), an extremely powerful side-channel attack capable of obtaining and analyzing statistical measurements across multiple operations. In addition, we […]
An exponential rise in data volume, and the meteoric rise of advanced workloads like AI/ML training, requires constant innovation in all aspects of computing. Memory bandwidth is a critical enabler of unleashing the power of processors and accelerators, and the High Bandwidth Memory (HBM) standard has evolved rapidly to deliver the performance required by the most demanding applications. For current generation HBM2E, Rambus […]
Highlights: Provides HBM3-ready memory subsystem solution consisting of fully-integrated PHY and digital controller Supports data rates up to 8.4 Gigabits per second (Gbps), enabling terabyte-scale bandwidth accelerators for artificial intelligence/machine learning (AI/ML) and high-performance computing (HPC) applications Leverages market-leading HBM2/2E experience and installed-base to speed implementation of customer designs using next-generation HBM3 memory SAN JOSE, […]
Thanks to everyone who joined us for Rambus Design Summit 2021. Over the coming weeks we’ll highlight the webinars and panels from the event all available now on-demand. About Frank Ferro Frank Ferro is the senior director of product management at Rambus Inc. responsible for memory interface IP products. Having spent more than 20 years […]
An exponentially rising tide of data has led to the development of application-specific silicon to tackle the requirements of demanding workloads such as AI/ML training, Advanced Driver Assistance Systems (ADAS) for automotive, network graphics and HPC. To keep these processors and accelerators fed requires state-of-the-art memory solutions that deliver extremely high bandwidth. Frank Ferro will […]
Joseph Rodriguez, senior product marketing engineer for IP cores at Rambus, has written an article for Semiconductor Engineering that explores the company’s recent achievement of reaching 4 gigabits per second (Gbps) data rate with its HBM2E memory interface. The milestone – which was demonstrated in silicon – required mastering substantial signal integrity and power integrity […]
CXL Memory Initiative Enabling new memory tiers for breakthrough server performance Contact Us Data Center Challenges Data centers face three major memory challenges as roadblocks to greater performance and total cost of ownership (TCO). Data Center Memory Challenges The first of these is the limitations of the current server memory hierarchy. There is a three […]
Tewksbury, MA. and San Jose, Calif. – May 19, 2021 – Avery Design Systems, a leader in functional verification solutions, and Rambus Inc. (NASDAQ: RMBS), a provider of industry-leading chips and silicon IP making data faster and safer, announced today they are extending their long-term memory model and PCIe® Verification IP (VIP) collaboration. Rambus utilizes Avery’s high-quality, full-featured memory models to verify their memory […]
Frank Ferro, Senior Director Product Management at Rambus, recently penned an article for Semiconductor Engineering that takes a closer look at high bandwidth memory (HBM) and 2.5D (stacking) architecture for AI/ML training. As Ferro notes, the impact of AI/ML increases daily – impacting nearly every industry across the globe. “In marketing, healthcare, retail, transportation, manufacturing […]
Artificial Intelligence/Machine Learning (AI/ML) grows at a blistering pace. The size of the largest training models has passed 100 billion parameters and is on pace to hit a trillion in the next year. The impact of AI/ML is being felt across the industry landscape, in higher education, and in financial markets. Underpinning this growth is […]