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Found 299 Results
PCIe 6.0 Controller
https://www.rambus.com/interface-ip/pci-express/pcie6-controller/PCIe 6.3 Controller Contact Us The PCI Express® (PCIe®) 6.3 Controller is configurable and scalable controller IP designed for ASIC implementation. The controller supports the PCIe 6.3 specification, including 64 GT/s data rates, PAM4 signaling, FLIT mode, and L0p power state. The PCIe 6.3 architecture will be essential for SoC designers creating next-generation chips that […]
PCIe 5.0 Multi-port Switch
https://www.rambus.com/interface-ip/pci-express/pcie5-multi-port-switch/PCIe 5.0 Multi-port Switch Contact Us The PCIe 5.0 Multi-port Switch (formerly XpressSWITCH) is a customizable, multiport embedded Switch for PCIe designed for ASIC and FPGA implementations enabling the connection of one upstream port and up to 31 downstream ports. ContactProduct Brief How the PCIe 5.0 Multi-Port Switch Works The PCIe 5.0 Switch IP transparently […]
PCIe Switch for USB4
https://www.rambus.com/interface-ip/pci-express/pcie-switch-for-usb4/PCIe Switch for USB4 Contact Us The PCIe Switch for USB4 (formerly XpressSWITCH) is a customizable, embedded switch for PCI Express (PCIe) designed for implementations in USB4 devices. ContactProduct Brief How the PCIe Switch for USB4 Works A fully configurable fanout switch, the PCIe Switch for USB4 provides one upstream port and up to 31 […]
PCIe 3.1 Controller
https://www.rambus.com/interface-ip/pci-express/pcie3-controller/PCIe 3.1 Controller Contact Us The PCIe 3.1 Controller (formerly XpressRICH) is designed to achieve maximum PCI Express (PCIe) 3.1 performance with great design flexibility and ease of integration. It is fully compatible with the PCIe 3.1/3.0 specification. A PCIe 3.1 Controller with AXI (formerly XpressRICH-AXI) is also available. The controller delivers high-bandwidth and low-latency connectivity […]
Debug and Test Solutions
https://www.rambus.com/interface-ip/pci-express/debug-and-test-solutions/Debug and Test Solutions Contact Us Gen5HOST PCIe 5.0 Host Enabling Reference Platform for Prototyping & Development of PCIe 5.0 Devices and Applications. Contact Product Brief Gen5HOST Gen5HOST provides a platform for prototyping and developing PCIe 5.0 hardware and software. At the core of Gen5HOST is the Rambus PCIe 5.0 Switch IP running on a […]
PLDA and AnalogX Acquisitions Supercharge the Rambus CXL Memory Interconnect Initiative
https://www.rambus.com/blogs/plda-and-analogx-acquisitions-supercharge-the-rambus-cxl-memory-interconnect-initiative/Big changes are coming to the data center driven by an exponential rise in data volume and traffic. Disaggregation and composability would move us beyond the classic architecture of the server as the unit of computing. By separating the functional components of compute, memory, storage and networking into pools, composed on-demand to match the specific […]
The Ultimate Guide to HBM2E Implementation & Selection
https://www.rambus.com/blogs/hbm2e/This is the most comprehensive guide to selecting and implementing a HBM2E memory IP interface solution. Frank Ferro and Joseph Rodriguez, Senior Directors Product Management at Rambus, hosted a webinar at our Rambus Design Summit discussing HBM2 and HBM2E memory technology. There’s a lot of decisions that need to be made when you’re developing high […]
SK hynix launches first DDR5 DRAM
https://www.newelectronics.co.uk/electronics-news/sk-hynix-launches-first-ddr5-dram/230998/#new_tabSK hynix has announced the launch of the world’s first DDR5 DRAM, optimised for Big Data, Artificial Intelligence (AI), and machine learning (ML) as a next generation standard of DRAM.
World’s first DDR5 DRAM module has focus on power
https://www.eenewspower.com/news/worlds-first-ddr5-dram-module-has-focus-power#new_tabSK hynix is launching the world’s first DDR5 memory module, aimed at Big Data, Artificial Intelligence (AI), and machine learning (ML) with a key focus on power consumption. The DDR5 memory module is supports transfer rate of 4.8 to 5.6Gbit/s, 1.8 times faster than the previous generation, at 1.1V rather than 1.2V. This reduces the […]
PCIe 5 Drill-Down with Rambus’ Suresh Andani: Part 2
https://www.rambus.com/blogs/pcie-5-drill-down-with-rambus-suresh-andani-part-2/In part one of this three-part series, Semiconductor Engineering Editor in Chief Ed Sperling and Suresh Andani, Senior Director, Product Marketing and Business Development at Rambus, discussed the evolving PCIe specification. In this blog post, Sperling and Andani explore early market adoption of PCIe 5, as well as the networking environment the specification will support […]
