At Rambus, we create cutting-edge semiconductor and IP products, spanning memory and interfaces to security, smart sensors and lighting.
Found 296 Results
PCIe 3.1 Controller
https://www.rambus.com/interface-ip/pci-express/pcie3-controller/PCIe 3.1 Controller Contact Us The PCIe 3.1 Controller (formerly XpressRICH) is designed to achieve maximum PCI Express (PCIe) 3.1 performance with great design flexibility and ease of integration. It is fully compatible with the PCIe 3.1/3.0 specification. A PCIe 3.1 Controller with AXI (formerly XpressRICH-AXI) is also available. The controller delivers high-bandwidth and low-latency connectivity […]
Debug and Test Solutions
https://www.rambus.com/interface-ip/pci-express/debug-and-test-solutions/Debug and Test Solutions Contact Us INSPECTOR for PCIe 5.0 Interposer Card for Diagnostic Testing, Exercising and Debug of PCIe Devices at up to Gen5 32 GT/s speed. ContactProduct Brief Inspector for PCIe 5.0 INSPECTOR is a PCIe 5.0-compliant interposer module designed for non-intrusive monitoring, diagnostic, exercising and debug of PCIe devices. INSPECTOR uses transparent switching […]
PLDA and AnalogX Acquisitions Supercharge the Rambus CXL Memory Interconnect Initiative
https://www.rambus.com/blogs/plda-and-analogx-acquisitions-supercharge-the-rambus-cxl-memory-interconnect-initiative/Big changes are coming to the data center driven by an exponential rise in data volume and traffic. Disaggregation and composability would move us beyond the classic architecture of the server as the unit of computing. By separating the functional components of compute, memory, storage and networking into pools, composed on-demand to match the specific […]
The Ultimate Guide to HBM2E Implementation & Selection
https://www.rambus.com/blogs/hbm2e/This is the most comprehensive guide to selecting and implementing a HBM2E memory IP interface solution. Frank Ferro and Joseph Rodriguez, Senior Directors Product Management at Rambus, hosted a webinar at our Rambus Design Summit discussing HBM2 and HBM2E memory technology. There’s a lot of decisions that need to be made when you’re developing high […]
SK hynix launches first DDR5 DRAM
https://www.newelectronics.co.uk/electronics-news/sk-hynix-launches-first-ddr5-dram/230998/#new_tabSK hynix has announced the launch of the world’s first DDR5 DRAM, optimised for Big Data, Artificial Intelligence (AI), and machine learning (ML) as a next generation standard of DRAM.
World’s first DDR5 DRAM module has focus on power
https://www.eenewspower.com/news/worlds-first-ddr5-dram-module-has-focus-power#new_tabSK hynix is launching the world’s first DDR5 memory module, aimed at Big Data, Artificial Intelligence (AI), and machine learning (ML) with a key focus on power consumption. The DDR5 memory module is supports transfer rate of 4.8 to 5.6Gbit/s, 1.8 times faster than the previous generation, at 1.1V rather than 1.2V. This reduces the […]
PCIe 5 Drill-Down with Rambus’ Suresh Andani: Part 2
https://www.rambus.com/blogs/pcie-5-drill-down-with-rambus-suresh-andani-part-2/In part one of this three-part series, Semiconductor Engineering Editor in Chief Ed Sperling and Suresh Andani, Senior Director, Product Marketing and Business Development at Rambus, discussed the evolving PCIe specification. In this blog post, Sperling and Andani explore early market adoption of PCIe 5, as well as the networking environment the specification will support […]
PCIe 5 Drill-Down with Rambus’ Suresh Andani: Part 1
https://www.rambus.com/blogs/pcie-5-drill-down-with-rambus-suresh-andani-part-1/Semiconductor Engineering Editor in Chief Ed Sperling recently sat down with Suresh Andani, Senior Director, Product Marketing and Business Development at Rambus, to discuss the evolution of PCIe and its latest iteration: PCIe 5. As Andani notes, PCIe 5 and subsequent iterations of the PCIe standard will continue to be one of the “key interfaces” […]
High-Performance Memory for AI/ML and HPC: Part 1
https://www.rambus.com/blogs/high-performance-memory-for-ai-ml-and-hpc-part-1/Semiconductor Engineering Editor in Chief Ed Sperling recently spoke with Rambus Sr. Director of Product Management Frank Ferro about designing high-performance memory subsystems for artificial intelligence (AI), machine learning (ML), and high-performance computing (HPC) applications. As Ferro notes, there is plenty of compute (CPU) power available today to support the above-mentioned markets. “[However], the advances […]
The Thermal Challenges of Moore’s Law: Part 2
https://www.rambus.com/blogs/the-thermal-challenges-of-moores-law-part-2/In part one of this two-part blog series, Semiconductor Engineering editor in chief Ed Sperling spoke with Steven Woo, Rambus fellow and distinguished inventor, about the relationship between Moore’s Law and the thermal challenges faced by the semiconductor industry. Specifically, Woo highlighted how the breakdown of Dennard scaling around 2005 prompted GPU designers to place […]
