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Found 299 Results
PCIe 5 Drill-Down with Rambus’ Suresh Andani: Part 1
https://www.rambus.com/blogs/pcie-5-drill-down-with-rambus-suresh-andani-part-1/Semiconductor Engineering Editor in Chief Ed Sperling recently sat down with Suresh Andani, Senior Director, Product Marketing and Business Development at Rambus, to discuss the evolution of PCIe and its latest iteration: PCIe 5. As Andani notes, PCIe 5 and subsequent iterations of the PCIe standard will continue to be one of the “key interfaces” […]
High-Performance Memory for AI/ML and HPC: Part 1
https://www.rambus.com/blogs/high-performance-memory-for-ai-ml-and-hpc-part-1/Semiconductor Engineering Editor in Chief Ed Sperling recently spoke with Rambus Sr. Director of Product Management Frank Ferro about designing high-performance memory subsystems for artificial intelligence (AI), machine learning (ML), and high-performance computing (HPC) applications. As Ferro notes, there is plenty of compute (CPU) power available today to support the above-mentioned markets. “[However], the advances […]
The Thermal Challenges of Moore’s Law: Part 2
https://www.rambus.com/blogs/the-thermal-challenges-of-moores-law-part-2/In part one of this two-part blog series, Semiconductor Engineering editor in chief Ed Sperling spoke with Steven Woo, Rambus fellow and distinguished inventor, about the relationship between Moore’s Law and the thermal challenges faced by the semiconductor industry. Specifically, Woo highlighted how the breakdown of Dennard scaling around 2005 prompted GPU designers to place […]
Memory Systems for AI: Part 6
https://www.rambus.com/blogs/memory-systems-for-ai-part-6/In part 5 of this series, we discussed the most common memory systems that are used in the highest performance AI applications. These include on-chip memory, high bandwidth memory (HBM) and Graphics DDR SDRAM (GDDR SDRAM). In this blog post, we’ll take an in-depth look at on-chip memory, as well as explore some of the […]
PCIe 4.0 Controller
https://www.rambus.com/interface-ip/pci-express/pcie4-controller/PCIe 4.0 Controller Contact Us The PCIe 4.0 Controller (formerly XpressRICH) is designed to achieve maximum PCI Express® (PCIe®) 4.0 performance with great design flexibility and ease of integration. It is fully backward compatible with PCIe 3.1/3.0. A PCIe 4.0 Controller with AXI (formerly XpressRICH-AXI) is also available. The controller delivers high-bandwidth and low-latency connectivity for […]
Protocol-IP-197
https://www.rambus.com/security/protocol-engines/protocol-ip-197/Protocol-IP-197 Multi-Protocol Engine with Classifier, Inline and Look-Aside, 10-100 Gbps Contact Us The Protocol-IP-197 Multi-Protocol Engine is an IP family for accelerating IPSec, SSL, TLS, DTLS (CAPWAP), 3GPP and MACsec up to 5, 10, 20, 40, 50 and 100 Gbps in multi-core server, communication or network processors offering a large selection of cipher algorithms. Designed for fast […]
Protocol-IP-196
https://www.rambus.com/security/protocol-engines/protocol-ip-196/Protocol-IP-196 Multi-Protocol Engine with Classifier, Look-Aside, 5-10 Gbps Contact Us The Protocol-IP-196 Multi-Protocol Engine is a protocol-aware packet engine for accelerating IPSec, SSL/TLS, DTLS, 3GPP and MACsec up to 10 Gbps in multi-core application or communication processors offering a large selection of cipher algorithms. Designed for fast integration, maximum CPU offload and offering full transforms, it […]
PCIe 5.0 Controller
https://www.rambus.com/interface-ip/pci-express/pcie5-controller/PCIe 5.0 Controller Contact Us The Rambus PCIe 5.0 Controller (formerly XpressRICH from PLDA) is designed to achieve maximum PCI Express® (PCIe®) 5.0 performance with great design flexibility and ease of integration. It is fully backward compatible with PCIe 4.0 and 3.1/3.0. A PCIe 5.0 Controller with AXI (formerly XpressRICH-AXI) is also available. The controller […]
Data Security on AI Chips: Hard to protect? (Interview)
https://www.rambus.com/blogs/data-security-ai-chips/Rambus fellow Helena Handschuh recently participated in a Semiconductor Engineering industry panel discussion about securing data running on AI/ML silicon. As the panel participants note, AI systems are designed to process data at high speeds, not limit access. This is precisely why the semiconductor industry is struggling to more effectively secure AI/ML data and prevent […]
Rambus Completes Acquisition of Northwest Logic, Extending Leadership in Interface IP
https://www.rambus.com/rambus-completes-acquisition-of-northwest-logic-extending-leadership-in-interface-ip/Highlights: Digital controller IP complements existing portfolio of high-speed interface PHYs Expands solutions for automotive, data center, artificial intelligence (AI), machine learning (ML) and communications applications Combined offerings, including HBM2, GDDR6, DDR4 and PCI Express (PCIe), create one-stop-shop for SoC designers SUNNYVALE, Calif. – Aug. 27, 2019 – Rambus Inc. (NASDAQ: RMBS), a premier silicon […]
