Found 24 Results

The Thermal Challenges of Moore’s Law: Part 2

https://www.rambus.com/blogs/the-thermal-challenges-of-moores-law-part-2/

In part one of this two-part blog series, Semiconductor Engineering editor in chief Ed Sperling spoke with Steven Woo, Rambus fellow and distinguished inventor, about the relationship between Moore’s Law and the thermal challenges faced by the semiconductor industry. Specifically, Woo highlighted how the breakdown of Dennard scaling around 2005 prompted GPU designers to place […]

The Thermal Challenges of Moore’s Law: Part 1

https://www.rambus.com/blogs/the-thermal-challenges-of-moores-law-part-1/

Semiconductor Engineering editor in chief Ed Sperling spoke with Steven Woo, Rambus fellow and distinguished inventor, about the relationship between Moore’s Law, Dennard scaling and thermal challenges. As Woo notes, there is a “tug of war” between the benefits that Moore’s Law provides and the breakdown of Dennard scaling in 2005. “Systems now need to […]

Memory a Key Enabler of Continued Advancement of AI/ML

https://www.rambus.com/blogs/memory-a-key-enabler-of-continued-advancement-of-ai-ml/

Recently Rambus fellow and distinguished inventor, Steve Woo, had a web chat with Bill Wong, technology editor for Electronic Design, to discuss some of the latest hardware trends in AI/ML. This was part of an ongoing conversation Steve and Bill have had regarding leading-edge developments in the AI/ML revolution. In the webcast, Steve discusses some […]

Memory Systems for AI: Part 2

https://www.rambus.com/blogs/memory-systems-for-ai-part-2/

In part one of this series, we discussed how the world’s digital data is growing exponentially, doubling approximately every two years. In fact, there’s so much digital data in the world that artificial intelligence (AI) is practically the only way to begin to make sense of it all in a timely fashion. Insights gleaned from […]

Memory Systems for AI: Part 1

https://www.rambus.com/blogs/memory-systems-for-ai-part-1/

Written by Steven Woo for Rambus Press There has been quite a lot of recent news about domain-specific processors that are being designed for the artificial intelligence (AI) market. Interestingly, many of the techniques used today in modern AI chips and applications have actually been around for several decades. However, neural networks didn’t really take […]

Closing the AI Memory Performance Gap

https://www.electronicdesign.com/webcasts/webinar-closing-ai-memory-performance-gap#new_tab

With Moore’s Law slowing and Dennard scaling finished, the industry has turned to domain-specific silicon to improve performance and power consumption. Learn some of these challenges, as well as potential ways to support the continued progress of AI silicon.

An Introduction to HPC computing

https://www.rambus.com/blogs/an-introduction-to-hpc-computing/

Written by Steven Woo Dominated by the United States, Japan and China, the high-performance computing (HPC) space is driven by an insatiable demand for ever-higher performance and greater power efficiency. With each new supercomputer debut, the above-mentioned trio sets progressively higher bars with the goal of capturing the highest Top500 score. Summit, Sierra and Sunway […]

Part 2: DRAM goes cryogenic

https://www.rambus.com/blogs/part-2-dram-goes-cryogenic/

In part one of this series, Rambus Chief Scientist Craig Hampel told Semiconductor Engineering’s Ed Sperling that cryogenic DRAM (below minus−180 °C or 93.15 kelvin) offers numerous power and performance advantages. These include increased transistor performance, the elimination of leakage, wires that super conduct, the ability of DRAM to operate as a non-volatile device and […]

Understanding the SerDes – Terabit Ethernet connection

https://www.rambus.com/blogs/understanding-the-serdes-terabit-ethernet-connection/

Mohit Gupta, senior director of product marketing for Rambus’ Memory and Interfaces Division, recently penned an article for Semiconductor Engineering that explores the connection between SerDes and terabit Ethernet. According to Gupta, 400 Gigabit Ethernet (400GbE) and 200 Gigabit Ethernet (200GbE) are currently slated for official release by the IEEE P802.3cd Task Force in December 2017. “Although there is not […]

Understanding the role of buffer chips in the evolving data center

https://www.rambus.com/blogs/understanding-the-role-of-buffer-chips-in-the-evolving-data-center/

Rambus VP of Systems and Solutions Steven Woo recently penned an article for ChipEstimate about the changing data center. According to Woo, the evolution of computing from the PC-centric world of the 1980’s-1990’s to today’s mobile+cloud environment has been a primary driver for change in processors, memory, storage and networks. Clock speeds and the breakdown […]