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CXL 3.0 Controller Contact Us The Rambus Compute Express Link (CXL) 3.0 Controller is a parameterizable design for ASIC and FPGA implementations. It leverages the Rambus PCIe 6.0 Controller architecture for the CXL.io protocol and adds the CXL.cache and CXL.mem protocols specific to CXL. The controller exposes a native Tx/Rx user interface for CXL.io traffic […]
HBM3 Controller Contact Us The Rambus HBM3 controller core is designed for use in applications requiring high memory bandwidth and low latency including AI/ML, HPC, advanced data center workloads and graphics. Secure Site Login ContactProduct Brief The HBM3 Memory Subsystem HBM3 is a high-performance memory that features reduced power consumption and a small form factor. […]
Introduction What’s new about PCI Express 5 (PCIe 5)? The latest PCI Express standard, PCIe 5, represents a doubling of speed over the PCIe 4.0 specifications. We’re talking about 32 Gigatransfers per second (GT/s) vs. 16GT/s, with an aggregate x16 link duplex bandwidth of almost 128 Gigabytes per second (GB/s). This speed boost is needed […]
Highlights: Bring FPGAs with a state-of-the-art offering of security IP products Secures the broad range of FPGAs from high-performance accelerators to low-power, lightweight devices Supports FPGAs serving applications for the Data Center, Artificial Intelligence / Machine Learning, Edge, IoT, Defense, and more SAN JOSE, Calif. – Aug. 22, 2023 – Rambus Inc. (NASDAQ: RMBS), a premier chip and […]
We have said it before, and we will say it again, you can never have enough memory bandwidth. Nowhere is this statement truer than in the data center where advanced workloads for high-performance computing (HPC) and artificial intelligence/machine learning (AI/ML) continue to demand unprecedented levels of bandwidth, and then some more. DDR5 memory is set […]
Last updated on: December 19, 2022 In this blog post, we take an in-depth look at Compute Express Link ™ (CXL™), an open standard cache-coherent interconnect between processors and accelerators, smart NICs, and memory devices. We explore how CXL is helping data centers more efficiently handle the yottabytes of data generated by artificial intelligence (AI) […]
The fifth annual AI Hardware Summit was back this month, and for the first time in a couple of years, it took place fully in-person in Santa Clara, California. The world’s leading experts in AI hardware came together over the course of three days to discuss some of the big challenges facing the industry, and […]
FIPS Crypto Library Contact Us The Rambus FIPS Crypto Library is a modern cryptographic library which offers up-to-date implementations of all major cryptographic algorithms and primitives. The FIPS Crypto Library contains a FIPS validated crypto module, a standard crypto library for non FIPS algorithms and a crypto API for easy use and integration. The FIPS […]
Rambus Fellow, Steven Woo, returns to the Rambus Design Summit stage tomorrow, and we are so excited for his keynote: Advancing Computing in the Accelerator Age! In our last interview before the show, we met with Steven to chat about his background, CXL, and some of the biggest challenges for computing in the years ahead. Read […]
1G to 50G Single-Port MACsec Engine with xMII interface and TSN support Contact Us The MACsec-IP-361 is a plug-and-play solution for adding MACsec on the xMII side of an Ethernet subsystem. It is ISO 26262 ASIL-B Ready certified and ideally positioned for designs where the MAC function is tightly integrated with the system-side, for example […]