R+™ LPDDR3 DRAM

The R+LPDDR3 DRAM brings next-generation, low-power performance to the market today. The R+ LPDDR3 DRAM is optimized for mobile applications and is fully-compliant with LPDDR3 and LPDDR3e specifications. When paired with the R+ LPDDR3 PHY, the DRAM supports data rates of up to 2400 Mbps, while providing an active power reduction of up to 30% when compared to a standards-only LPDDR3 device at equivalent speed.

  • Fully-compliant with industry standard LPDDR3 and LPDDR3e
  • R+™ enhanced mode maintains compatibility with existing infrastructure while improving data rate or power consumption
  • Up to 30% lower DRAM active power (IDD4R) versus standard LPDDR3
  • Supports data rates up to 2400 Mbps and 9.4 GB/sec bandwidth per channel
  • Compatible with standard LPDDR3 PHYs

LPDDR3 DRAM block diagram



FEATURESLPDDR3LPDDR3eR+ LPDDR3
Standards HSUL HSUL HSUL/LVSTL
Data Rates (Mbps) 333-1600 333-2133 333-2400
Density (Gb) 4 / 8 / 16 / 32 4 / 8 / 16 / 32 4 / 8 / 16 / 32
Data Path Width x16 / x32 x16 / x32 x16 / x32
VDD (V) 1.8 / 1.2 / 1.2 1.8 / 1.2 / 1.2 1.8 / 1.2 / 1.2
Rank Support 2 2 2
Package POP, MCP, FBGA POP, MCP, FBGA POP, MCP, FBGA
  • Fully-compliant with industry standard LPDDR3e and LPDDR3
  • Compatible with standard LPDDR3 controller PHYs. No memory controller changes required
  • Scalable architecture supports data rates up to 2400 Mbps and 9.4 GB/sec bandwidth per channel
  • Flexible packaging options (POP, MCP, FBGA)
  • Full compatibility to LPDDR3e/LPDDR3 low-power states
  • Support data path widths of 16 and 32 bits
  • DRAM densities from 4Gb to 32Gb
  • Dual rank support
  • LVSTL(1) enhanced signaling mode available to enable data rates of 2400 Mbps and beyond. No system hard-ware changes needed to support LVSTL
  • Up to 30% lower DRAM active power
  • Up to 25% lower active memory system power
  • Deep Power-down support
  • Refresh, self-refresh, and partial array self-refresh support
  • On-die programmable VrefDQ generation
  • Programmable output impedance, on-die termination, and periodic ZQ calibration
  • CA eye training, DQS write leveling and DQ read calibration support
  • On-Die-Termination support

Memory Suppliers/Manufacturers

  • Complete specification and implementation package
  • Reference design database including schematics and matching layout
  • Integration guidelines
  • Package and PCB design guidelines
  • Logic and power simulations
  • Timing verification environment
  • Device characterization and test environment
  • Optional design integration and bring-up support services

 

SOC/ASIC Developers

  • Contact R+ LPDDR3 memory supplier for datasheet, roadmap, schedule, and pricing

 


 

 

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