Edge
Catching a tidal wave of data
Speeding data streams
High-speed interconnects create the data highway for the high-speed communications between edge devices, end points and the data centers at the core. Rambus chip-to-chip (SerDes) and memory interfaces enable high performance data transfer to keep real-time app processing humming. We offer a broad range of flexible solutions for SoC and system designers building the next generation of edge devices.
High Speed Memory Interface Chipsets Let Server Performance Fly
The demands on server performance continue to increase at a tremendous pace. New requirements from large in-memory databases that are powering today’s cloud services and advanced analytics tools are arriving just as the impact of Moore’s Law is starting to slow. One key new opportunity is for high-speed server memory interface chipsets, which enable high-speed memory performance without compromising on memory capacities. Companies looking to optimize their server memory architecture designs, and improve their overall server performance and reliability, should give serious consideration to optimized DDR4 memory interface chipsets, which enhance the performance of server memory modules.
Providing robust device security
Edge devices handle data of great value to consumers and businesses. Safeguarding the precious data processed and communicated by edge devices requires a multi-tiered approach and a security-by-design philosophy. The CryptoManager Root of Trust can be embedded as a secure processing core alongside the main CPU to provide robust edge device security, while CryptoManager infrastructure manages the provisioning and management of cryptographic keys at the time of manufacture and in the field.
Introduction to Side-Channel Attacks
Side-channel attacks, including simple power analysis and differential power analysis, conducted against electronic gear are relatively simple and inexpensive to execute. An attacker does not need to know specific implementation details of the cryptographic device to perform these attacks and extract keys. As all physical electronic systems routinely leak information, effective side-channel countermeasures should be implemented at the design stage to ensure protection of sensitive keys and data.