Forward Error Correction (FEC) IP Cores

Ensuring a glitch-free visual experience for DisplayPort and HDMI applications using VESA DSC

DisplayPort and HDMI Forward Error Correction IP

Rambus DisplayPort™ 1.4 and HDMI® 2.1 FEC IP cores deliver a glitch-free visual experience for end users, while enabling designers to use VESA® Display Stream Compression (DSC) to reach higher resolutions and refresh rates.

Solution Product Brief Description
DisplayPort 1.4 FEC Transmitter (Tx) Download the DisplayPort 1.4 FEC Transmitter (Tx) product brief Solution for GPUs, UHD Set-top Boxes, Desktop and Laptop PCs, USB-C/DisplayPort Accessories
DisplayPort 1.4 FEC Transmitter (Tx) ASIL-B Download the DisplayPort 1.4 FEC Transmitter (Tx) ASIL-B product brief ASIL-B certified solution for automotive applications
DisplayPort 1.4 FEC Receiver (Rx) Download the DisplayPort 1.4 FEC Receiver (Rx) product brief Solution for High-Performance External Displays, UHD TV, USB-C/DisplayPort Accessories
HDMI 2.1 FEC Transmitter (Tx) Download the HDMI 2.1 FEC Transmitter (Tx) product brief Solution for GPUs, Desktop and Laptop PCs, UHD Set-top Boxes, Pro AV, HDMI 2.1 Accessories
HDMI 2.1 FEC Receiver (Tx) Download the HDMI 2.1 FEC Receiver (Tx) product brief Solution for UHD Monitors, UHD TVs and Home Theaters, Pro AV, HDMI 2.1 Accessories

DisplayPort 1.4 and HDMI 2.1 FEC IP

FeatureDisplayPort 1.4HDMI 2.1
Reed Solomon (RS) FECRS (254,250)
10-bit symbols
RS (255,251)
8-bit symbols
Lane Operation1, 2 and 4-lane modes
NB: 4-lane mode requires 2 FEC IP core instances
3-lane and 4-lane modes
Statistics InterfaceIncluded in RxIncluded in Rx
DP Main 8b/10b EncoderTx: Included
Rx: Optional
 

Using Forward Error Correction with VESA DSC Compression

Bit errors on an uncompressed video stream have no visual impact. However, bit errors on a compressed video stream result in an impaired visual experience for a user. For this reason, DisplayPort 1.4 and HDMI 2.1 mandate the use of Reed Solomon (RS) FEC when enabling VESA DSC.

For example, DisplayPort 1.4 has a bit error rate (BER) of 10-9 without FEC. The BER is the probability that a given bit will be corrupted. With the use of FEC, the BER is lowered to 10–18. At full DisplayPort bandwidth (32.4Gbps), this represents approximately one uncorrected error per year.

Example of the Rambus VESA DSC and FEC IP cores used within a DisplayPort 1.4 subsystem
Example of the Rambus VESA DSC and FEC IP cores used within a DisplayPort 1.4 subsystem
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