Rambus VESA® Display Stream Compression (DSC) and VDC-M encoder and decoder IP cores deliver visually lossless video compression performance, enabling designers to handle the growing bandwidth requirements of cutting-edge displays with higher resolutions, faster refresh rates, and greater pixel depths.
|Encoder AMD FPGAs
|Decoder AMD FPGAs
|Encoder Intel FPGAs
|Decoder Intel FPGAs
|Encoding Block Structure
|Visually Lossless Performance (bits per pixel)
|Bits Per Video Component
Example: UHD 3840 x 2160
|RGB and YCbCR 4:4:4
The Rambus VESA DSC and VDC-M IP cores deliver visually lossless video compression for mobile, AR/VR and automotive display applications.
The VESA DSC IP cores can compress any image to 8 bits per pixel (bpp), which results in a 3X compression ratio for a 24 bpp image or a 3.75X compression ratio for a 30 bpp image. The VDC-M cores use more sophisticated video encoding tools to achieve even higher compression factors for applications that require even more compression. VDC-M can reduce a 30 bpp uncompressed image to 6 bpp, and in some use cases, it can be visually lossless at a 6X compression ratio.
The VESA DSC and VDC-M IP cores can be combined with the Rambus MIPI DSI-2 Controller cores, and your choice of C/D-PHY, to form a complete display solution.
MIPI® Alliance technology has helped enable the dramatic growth of the mobile phone market. The function and capabilities of MIPI interface solutions have grown dramatically as well. MIPI DSI-2SM has become the leading display interface across a growing range of products including smartphones, AR/VR, IoT appliances and ADAS/autonomous vehicles. As the application space has expanded, so too have the performance requirements. Learn how MIPI DSI-2 interface and VESA® DSC visually lossless compression technologies can meet the challenges of next-generation displays.
VESA DSC Encoder & Decoder
VESA VDC-M Encoder & Decoder