Rambus Blog
MACsec Explained: From A to Z
From A to Z, learn everything you need to know about Media Access Control Security (also known as MACsec). For
High-Performance Memory for AI/ML and HPC: Part 2
In part one of this two-part series, Semiconductor Engineering Editor in Chief Ed Sperling and Rambus Sr. Director of Product
High-Performance Memory for AI/ML and HPC: Part 1
Semiconductor Engineering Editor in Chief Ed Sperling recently spoke with Rambus Sr. Director of Product Management Frank Ferro about designing
Rambus Launches 800G MACsec Multi-Channel Engine
Ethernet has become the ubiquitous communication solution from the desktop to the carrier network. In data centers at the heart
The Thermal Challenges of Moore’s Law: Part 2
In part one of this two-part blog series, Semiconductor Engineering editor in chief Ed Sperling spoke with Steven Woo, Rambus
The Thermal Challenges of Moore’s Law: Part 1
Semiconductor Engineering editor in chief Ed Sperling spoke with Steven Woo, Rambus fellow and distinguished inventor, about the relationship between
Memory a Key Enabler of Continued Advancement of AI/ML
Recently Rambus fellow and distinguished inventor, Steve Woo, had a web chat with Bill Wong, technology editor for Electronic Design,
Post-Quantum Crypto and Rambus
Today’s encryption methods are generally broken down into two types: symmetric and asymmetric. Symmetric encryption relies on the sender and
Memory Systems for AI: Part 6
Written by Steven Woo for Rambus Press In part 5 of this series, we discussed the most common memory systems
Memory Systems for AI: Part 5
Written by Steven Woo for Rambus Press In part four of this series, we took a closer look at the
Memory Systems for AI: Part 4
Written by Steven Woo for Rambus Press In part three of this series, we discussed how a Roofline model can
Memory Systems for AI: Part 3
Written by Steven Woo for Rambus Press In part two of this series, we took a closer look at how
Complete Memory Interface Solution for HBM2E Launched
Rambus has announced a comprehensive interface solution for HBM2E memory consisting of co-verified PHY and memory controller. Operating at a
Memory Systems for AI: Part 2
In part one of this series, we discussed how the world’s digital data is growing exponentially, doubling approximately every two
Memory Systems for AI: Part 1
Written by Steven Woo for Rambus Press There has been quite a lot of recent news about domain-specific processors that
Cable Haunt vulnerability can give hackers remote access to approximately 200 million cable modems
Danish cybersecurity experts Alexander Krog, Jens Stærmose and Kasper Terndrup of cybersecurity firm Lyrebirds ApS, and independent Danish researcher Simon
PCI Express 5 vs. 4: What’s New? [Everything You Need to Know]
Introduction What’s new about PCI Express 5 (PCIe 5)? The latest PCI Express standard, PCIe 5, represents a doubling of
California’s IoT law is a good start, but more needs to be done
Written by Paul Karazuba, head of product, Rambus Security Passed by former California governor Jerry Brown, cybersecurity law SB-327 is
Plundervolt steals keys from cryptographic algorithms
An international team of white hat researchers has successfully corrupted the integrity of Intel Software Guard Extensions (SGX) on Intel
Shattering the neural network memory wall with Checkmate
A recent paper published on arXiv by a team of UC Berkeley researchers observes that neural networks are increasingly bottlenecked
Complete Interface Solution for PCIe 5.0 Launched
Rambus has announced a comprehensive interface solution for PCI Express 5 (PCIe 5.0) consisting of a new PCIe 5.0 PHY