Rambus Blog
From Multilayer Perceptrons to GANs
Written by Steven Woo In our previous blog post,we discussed the history of neural networks (NNs) and machine learning (ML).
Reduced-Precision Computation for Neural Network Training
In our previous blog post, we discussed the process of training neural networks (NN) and briefly touched on NN training
Understanding ML and ANN memory requirements
Written by Steven Woo Artificial Neural Networks First proposed in 1944 by Warren McCullough and Walter Pitts, an artificial neural
Paul Kocher Awarded 2019 Marconi Prize
Every year, The Marconi Society recognizes those individuals who have made a significant contribution to the advancement of communications for
GDDR6 Crosstalk Article – Rambus
Director of Signal Integrity Engineering at Rambus, Shawn Nikoukary, recently published a piece in eeweb.com/EE Times about crosstalk (xtalk) as
EE Times Article Series Touts RISC-V
Rich Quinnell, veteran semiconductor industry reporter, has written an EE Times article with the headline, RISC-V on the Verge of
Uber eyes an AI future
Rick Merritt of the EE Times recently reported that Uber is using banks of Nvidia GPUs for deep learning applications. The
Mobile World Congress 2019: A payments perspective
Andre Stoorvogel, Director, Product Marketing, Rambus Payments For anyone attending Mobile World Congress last week, they have no doubt gone
You must embrace, threats from cyberspace, to your card-on-file database
You must embrace, threats from cyberspace, to your card-on-file database By Andre Stoorvogel, Rambus It is hard not to become
IDC White Paper Lays Out Future of Memories and Interfaces
A recently published IDC white paper calls attention to the growing significance of chip connectivity. Entitled, “Hidden Signals: The Memories
32G Multi-Protocol SerDes PHY Out the Gate
Hemant Dhulla, vice president and general manager of IP Cores at Rambus says that the newly announced 28G and 32G
HBM2 gets an upgrade as semiconductor industry eyes HBM3
JEDEC recently updated its JESD235 High Bandwidth Memory (HBM) DRAM standard. As we’ve previously discussed on Rambus Press, HBM DRAM
Wanted Bugs- Dead or Alive Reward- $3,000 to $100,000
Can you believe it? There are big bucks rewards for catching, capturing, and turning in villains we’ve come to know
2018 Top IT Security Stories, Meltdown and Spectre at the Top
Meltdown and Spectre microprocessor vulnerabilities took top billing in ComputerWeekly.com’s top 10 IT security stories of 2018. Discovery of these
Real-Time Payments and The Growing Obsolescence of Cash
David Worthington, VP, Payments at Rambus According to this year’s World Payments Report, compiled by Capgemini and BNP Paribas, the
GDDR6 DRAM Signal Integrity: Taking on The New Design Challenges
Signal integrity (SI) is a perennial issue with system and SoC designers. As design engineers begin to launch into next
Is Hardware-Based Security The Right Answer to Cloud Security?
Without question, today, there is considerable focus on securing the Cloud. This is especially true for virtualization systems, which have
When Real-Time Payments Go Wrong
David Worthington, VP, Payments at Rambus Since the 1980s, momentum behind real-time payments (RTP) – also known as faster or
Protecting Wi-Fi chipsets with hardware-based security cores
Embedi security researcher Denis Selianin recently disclosed a slew of major vulnerabilitiesthat impacted one of the most popular Wi-Fi chipsets
Get Ready for DDR5 DIMM Chipsets
Doug Daniels, Senior Manager, Applications Engineering at Rambus, recently penned an article for eeweb.com/EE Times, giving server/system designers a heads
The Next Vulnerability: Looking Back on Meltdown and Spectre One Year Later
Around this time last year, two vulnerabilities known as Meltdown and Spectre became public. Discovered independently by multiple research teams,