At Rambus, we create cutting-edge semiconductor and IP products, spanning memory and interfaces to security, smart sensors and lighting.
LPDDR Memory Controller IP
Rambus LPDDR5/5X and LPDDR4/4X digital controllers deliver high memory bandwidth and throughput for low power applications including mobile, automotive, Internet of Things (IoT), and edge networking devices.
| Version | Maximum Data Rate (Gbps) | Controller |
|---|---|---|
| LPDDR5/5X | 6.4 |  Product Brief |
| LPDDR4/4X | 3.2 | Product Brief |
LPDDR Controller IP
| Feature | LPDDR5 /LPDDR5X | LPDDR4/ LPDDR4X |
|---|---|---|
| Data Rate (Gbps) | 6.4 / 8.5 | 3.2 / 4.266 |
| Memory Clock Operation (MHz) | 800/1066 | 800/1066 |
| Device Densities (Per Channel Per Rank) | Up to and including 32Gb | Up to and including 16Gb |
| DQ Support | 16 or 32 bits | 32 bits |
| ECC Support | In-Line ECC (also Link ECC) | In-Line ECC |
| ECC Scrubber | Supported | Supported |
| Bank Management | Monitors status of each bank – 16 banks per rank monitored and helps minimize access delays | Monitors status of each bank – 8 banks per rank monitored and helps minimize access delays |
| Bank Refresh | Yes | Yes |
| Optimize Performance and Throughput | Queue-based User Interface with Built-in Reordering Scheduler | Queue-based User Interface with Add-on Reordering Scheduler |
| Parity Protection of Stored Registers | Yes | Yes |
| Look-ahead Activate, Precharge and Auto-Precharge Logic | Yes | Yes |
| PHY Interface | DFI 5.1 | DFI 5.0 |
| Multiple Ranks | Yes (up to 4) | Yes (up to 4) |
| WCK:CK Ratio | 4:1 | |
| CK:DFI_CLK Ratio | 1:1 | 2:1 |
| Mode Support | x16 and x8 | x16 |
| Data Bus Inversion (Read and/or Write) | Yes | Yes |
| Mode Register Write (MRW) and Mode Register Read (MRR) | Yes | Yes |
| Self-refresh and Power-down Modes | Yes | Yes |
| ZQ Calibration | Command-based (Manual and Automatic) and Background | Command-based (Manual or Automatic) |
| Add-On Cores | AXI Core Bus Interface Multi-Port Front-End In-Line ECC Advanced RMW Memory Test/Advanced Memory Test Memory Analyzer | AXI Core Bus Interface Multi-Port Front-End Reorder In-Line ECC RMW Memory Test Memory Analyzer |
LPDDR5 Memory Controller Operation
The LPDDR5 controller core accepts commands using a simple local interface and translates them to the command sequences required by LPDDR5 devices. The core also performs all initialization, refresh and power-down functions.
The core uses bank management logic to monitor the status of each LPDDR bank. Banks are only opened or closed when necessary, minimizing access delays.
The core queues up multiple commands in the command queue. This enables optimal bandwidth utilization for both short transfers to highly random address locations as well as longer transfers to contiguous address space. The command queue is also used to opportunistically perform look-ahead activates, precharges and auto-precharges further improving overall throughput.
Add-On Cores such as an AXI Core Bus Interface, Multi-Port Front-End and In-Line ECC Core can be optionally delivered with the core. The core is delivered fully integrated and verified with the target LPDDR5 PHY.
LPDDR5 Delivers High Bandwidth for a Growing Range of Applications
Initially designed for mobile phones and laptops, the bandwidth and low power characteristics of LPDDR make it an increasingly attractive choice of memory for applications in IoT, automotive, edge computing and the data center. Fifth-generation LPDDR5 raises data rates to 6.4 Gbps and bandwidth to 25.6 GB/s for a x32 DRAM device. In this session, Rambus and its partners OpenFive and Avery Design Systems will discuss their high-performance, high-quality, configurable LPDDR5 solution.
- Controller (source code)
- Testbench (source code)
- Complete documentation
- Expert technical support
- Maintenance updates
- Customization
- SoC Integration
