LPDDR Memory Controller IP

Delivering power-efficient, high-bandwidth memory performance

LPDDR Memory Controller IP

Rambus LPDDR5T/5X/5 and LPDDR4X/4 digital controllers deliver high memory bandwidth and throughput for low power applications including mobile, automotive, Internet of Things (IoT), laptop PCs and edge networking devices.

LPDDR Controller IP

Data Rate (Gbps)9.6 / 8.5 / 6.44.266 / 3.2
Memory Clock Operation (MHz)800/1066800/1066
Device Densities (Per Channel Per Rank)Up to and including 32GbUp to and including 16Gb
DQ Support16 or 32 bits32 bits
ECC SupportIn-Line ECC (also Link ECC)In-Line ECC
ECC ScrubberSupportedSupported
Bank ManagementMonitors status of each bank – 16 banks per rank monitored and helps minimize access delaysMonitors status of each bank – 8 banks per rank monitored and helps minimize access delays
Bank RefreshYesYes
Optimize Performance and ThroughputQueue-based User Interface with Built-in Reordering SchedulerQueue-based User Interface with Add-on Reordering Scheduler
Parity Protection of Stored RegistersYesYes
Look-ahead Activate, Precharge and Auto-Precharge LogicYesYes
PHY InterfaceDFI 5.1DFI 5.0
Multiple RanksYes (up to 4)Yes (up to 4)
WCK:CK Ratio4:1 
CK:DFI_CLK Ratio1:12:1
Mode Supportx16 and x8x16
Data Bus Inversion (Read and/or Write)YesYes
Mode Register Write (MRW) and Mode Register Read (MRR)YesYes
Self-refresh and Power-down ModesYesYes
ZQ CalibrationCommand-based (Manual and Automatic) and BackgroundCommand-based (Manual or Automatic)
Add-On CoresAXI Core Bus Interface
Multi-Port Front-End
In-Line ECC
Advanced RMW
Memory Test/Advanced Memory Test
Memory Analyzer
AXI Core Bus Interface
Multi-Port Front-End
In-Line ECC
Memory Test
Memory Analyzer

LPDDR5T/5X/5 Memory Controller Operation

The LPDDR5T/5X/5 controller core accepts commands using a simple local interface and translates them to the command sequences required by LPDDR5 devices. The core also performs all initialization, refresh and power-down functions.

The core uses bank management logic to monitor the status of each LPDDR bank. Banks are only opened or closed when necessary, minimizing access delays.

The core queues up multiple commands in the command queue. This enables optimal bandwidth utilization for both short transfers to highly random address locations as well as longer transfers to contiguous address space. The command queue is also used to opportunistically perform look-ahead activates, precharges and auto-precharges further improving overall throughput.

LPDDR5 Memory Interface Subsystem Block Diagram
LPDDR5T/5X/5 Memory Interface Subsystem Block Diagram

Add-On Cores such as an AXI Core Bus Interface, Multi-Port Front-End and In-Line ECC Core can be optionally delivered with the core. The core is delivered fully integrated and verified with the target LPDDR5 PHY.

LPDDR5X: Delivering High Bandwidth and Power Efficiency

Watch Webinar

The bandwidth and low power characteristics of LPDDR make it an increasingly attractive choice of memory for applications in IoT, automotive, and edge computing. LPDDR5X takes performance to the next level with a data rate of up to 8.5 Gbps. Join us to learn which applications can benefit from using LPDDR memory.

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