LPDDR Memory Controller IP

Delivering power-efficient, high-bandwidth memory performance

LPDDR Memory Controller IP

Rambus LPDDR5/5X and LPDDR4/4X digital controllers deliver high memory bandwidth and throughput for low power applications including mobile, automotive, Internet of Things (IoT), and edge networking devices.

VersionMaximum Data Rate (Gbps)Controller
LPDDR5/5X6.4Download LPDDR5 Product Brief Product Brief
LPDDR4/4X3.2Download LPDDR4 Product Brief Product Brief

LPDDR Controller IP

Data Rate (Gbps)6.4 / 8.53.2 / 4.266
Memory Clock Operation (MHz)800/1066800/1066
Device Densities (Per Channel Per Rank)Up to and including 32GbUp to and including 16Gb
DQ Support16 or 32 bits32 bits
ECC SupportIn-Line ECC (also Link ECC)In-Line ECC
ECC ScrubberSupportedSupported
Bank ManagementMonitors status of each bank – 16 banks per rank monitored and helps minimize access delaysMonitors status of each bank – 8 banks per rank monitored and helps minimize access delays
Bank RefreshYesYes
Optimize Performance and ThroughputQueue-based User Interface with Built-in Reordering SchedulerQueue-based User Interface with Add-on Reordering Scheduler
Parity Protection of Stored RegistersYesYes
Look-ahead Activate, Precharge and Auto-Precharge LogicYesYes
PHY InterfaceDFI 5.1DFI 5.0
Multiple RanksYes (up to 4)Yes (up to 4)
WCK:CK Ratio4:1 
CK:DFI_CLK Ratio1:12:1
Mode Supportx16 and x8x16
Data Bus Inversion (Read and/or Write)YesYes
Mode Register Write (MRW) and Mode Register Read (MRR)YesYes
Self-refresh and Power-down ModesYesYes
ZQ CalibrationCommand-based (Manual and Automatic) and BackgroundCommand-based (Manual or Automatic)
Add-On CoresAXI Core Bus Interface
Multi-Port Front-End
In-Line ECC
Advanced RMW
Memory Test/Advanced Memory Test
Memory Analyzer
AXI Core Bus Interface
Multi-Port Front-End
In-Line ECC
Memory Test
Memory Analyzer

LPDDR5 Memory Controller Operation

The LPDDR5 controller core accepts commands using a simple local interface and translates them to the command sequences required by LPDDR5 devices. The core also performs all initialization, refresh and power-down functions.

The core uses bank management logic to monitor the status of each LPDDR bank. Banks are only opened or closed when necessary, minimizing access delays.

The core queues up multiple commands in the command queue. This enables optimal bandwidth utilization for both short transfers to highly random address locations as well as longer transfers to contiguous address space. The command queue is also used to opportunistically perform look-ahead activates, precharges and auto-precharges further improving overall throughput.

LPDDR5 Memory Interface Subsystem Block Diagram
LPDDR5 Memory Interface Subsystem Block Diagram

Add-On Cores such as an AXI Core Bus Interface, Multi-Port Front-End and In-Line ECC Core can be optionally delivered with the core. The core is delivered fully integrated and verified with the target LPDDR5 PHY.

LPDDR5 Delivers High Bandwidth for a Growing Range of Applications

Watch Webinar

Initially designed for mobile phones and laptops, the bandwidth and low power characteristics of LPDDR make it an increasingly attractive choice of memory for applications in IoT, automotive, edge computing and the data center. Fifth-generation LPDDR5 raises data rates to 6.4 Gbps and bandwidth to 25.6 GB/s for a x32 DRAM device. In this session, Rambus and its partners OpenFive and Avery Design Systems will discuss their high-performance, high-quality, configurable LPDDR5 solution.

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