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At Rambus, we create cutting-edge semiconductor and IP products, spanning memory and interfaces to security, smart sensors and lighting.

PCI Express IP

Delivering high-bandwidth interconnect performance

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PCI Express Controller IP

Rambus silicon-proven, high-performance PCI Express® (PCIe®) 6.0, 5.0, 4.0 and earlier generation digital controllers are optimized for use in SoCs, ASICs and FPGAs. These market-leading solutions for high-performance interfaces address AI/ML, data center and edge applications.

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PCIe Controller
PCIe Debug and Test Solutions & Add-On Cores
PCIe Interconnect Subsystem
PCIe Switch, Retimer, DMA & USB4 IP
Version Maximum Data Rate (GT/s) Controller Controller with AXI
PCIe 6.0 64 Download PCIe 6.0 Controller Product Brief Product Brief Download PCIe 6.0 Controller with AXI Product Brief Product Brief
PCIe 5.0 32 Download PCIe 5.0 Controller Product Brief Product Brief Download PCIe 5.0 Controller with AXI Product Brief Product Brief
PCIe 4.0 16 Download PCIe 4.0 Controller Product Brief Product Brief Download PCIe 4.0 Controller with AXI Product Brief Product Brief
PCIe 3.1 8 Download PCIe 3.1 Controller Product Brief Product Brief Download PCIe 3.1 Controller with AXI Product Brief Product Brief
PCIe 2.1 5 Download PCIe 2.1 Controller Product Brief Product Brief Download PCIe 2.1 Controller with AXI Product Brief Product Brief

PCIe Controller IP

FeaturePCIe 6.0
Controller		PCIe 5.0
Controller		PCIe 4.0
Controller		PCIe 3.1
Controller		PCIe 2.1
Controller
Data Rate (GT/s)64321685
Data PathScalableScalableScalableScalableScalable
Topologies SupportedRoot Port
Endpoint
Switch Port
Dual-Mode		Root Port
Endpoint
Switch Port
Dual-Mode		Root Port
Endpoint
Switch Port
Dual-Mode		Root Port
Endpoint
Switch Port
Dual-Mode		Root Port
Endpoint
Switch Port
Dual-Mode
Duplex Lane Configurationsx1, x2, x4, x8, x16x1, x2, x4, x8, x16x1, x2, x4, x8, x16x1, x2, x4, x8, x16x1, x2, x4, x8, x16
Backward Compatibility5.0, 4.0, 3.1/3.04.0, 3.1/3.03.1/3.03.0/2.1/2.01.1/1.0
Clock Gating/Power GatingYes    
Advanced RASYesYesYesYesYes
Virtual Channel SupportFLIT and non-FLIT mode    
Forward Error Correction (FEC)Yes    
L0p Low Power ModeYes    
Optional FeaturesIDE Security,
AER,
ECRC,
ECC,
MSI,
MSI-X,
Multifunction,
Crosslink		AER,
ECRC,
ECC,
MSI,
MSI-X,
Multifunction,
Crosslink		AER,
ECRC,
ECC,
MSI,
MSI-X,
Multifunction,
Crosslink		AER,
ECRC,
ECC,
MSI,
MSI-X,
Multifunction,
Crosslink		AER,
ECRC,
ECC,
MSI,
MSI-X,
Multifunction,
Crosslink
P2P

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PCIe Switch, Retimer, DMA and USB4 IP

SolutionProduct BriefDescription
PCIe 6.0 Retimer ControllerDownload PCIe 6.0 Retimer Controller Product BriefPCIe 6.0 Retimer Controller with CXL Support Provides Highly Optimized, Low-latency Data Path for Signal Regeneration
PCIe 5.0 Multi-port SwitchDownload PCIe 5.0 Multi-port Switch Product Brief Customizable Multi-port Switch, Connects One Upstream Port to Up to 31 Downstream Ports
PCIe Controller for USB4Download PCIe Controller for USB4 Product Brief PCIe 5 Controller with USB4 Support, with Native Logic Interface Options
PCIe Controller for USB4 with AXIDownload PCIe Controller for USB4 with AXI Product Brief PCIe 5 Controller with USB4 Support, with AXI Logic Interface Options
PCIe Switch for USB4Download PCIe Switch for USB4 Product Brief Customizable Switch with USB4 Support, Connects One Upstream Port to Up to 31 Downstream Ports

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PCIe Debug and Test Solutions, and Add-On Cores

SolutionProduct BriefDescription
INSPECTOR for PCIe 5.0Download INSPECTOR for PCIe 5.0 Product Brief Interposer Card for Diagnostic Testing, Exercising and Debug of PCIe Devices at up to 32 GT/s
Gen5HOSTDownload the Gen5HOST Product Brief Host Enabling Reference Platform for Prototyping and Development of PCIe 5.0 Devices and Apps
Gen5ENDPOINTDownload the Gen5ENDPOINT Product Brief Endpoint Reference Platform for Prototyping and Development of PCIe 5.0 Devices
XpressAGENTDownload the XpressAGENT Product Brief Add-on Core Simplifies Observability and Expedites Debugging of PCIe and CXL subsystems

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PCIe 6.0 Interconnect Subsystem

The Rambus PCIe 6.0 Controller exposes a highly efficient transmit (Tx) and receive (Rx) interface with configurable bus widths. Designed to satisfy a multitude of customer and industry use cases, the IP can be configured to support endpoint, root port, switch port, and dual-mode topologies, allowing for a variety of use models. The provided Graphical User Interface (GUI) Wizard allows designers to tailor the IP to their exact requirements, by enabling, disabling, and adjusting a vast array of parameters.

PCIe 6.0 Interface Subsystem
PCIe 6.0 Interface Subsystem

Rambus provides integration and validation of the PCIe 6.0 digital controller with the customer’s choice of 3rd-party PCIe 6.0 PHY.

Data Center Evolution: The Leap to 64 GT/s Signaling with PCI Express 6.0

Data Center Evolution: The Leap to 64 GT/s Signaling with PCI Express 6.0

The PCIe interface is the critical backbone that moves data at high bandwidth and low latency between various compute nodes such as CPUs, GPUs, FPGAs, and workload-specific accelerators. With the torrid rise in bandwidth demands of advanced workloads such as AI/ML training, PCIe 6.0 jumps signaling to 64 GT/s with some of the biggest changes yet in the standard. 

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