Home > Interface IP > PCI Express Interconnect Subsystem IP
Version | Maximum Data Rate (GT/s) | Subsystem | Controller | Controller with AXI | PHY |
---|---|---|---|---|---|
PCIe 6.0 | 64 | ||||
PCIe 5.0 | 32 | ||||
PCIe 4.0 | 16 | ||||
PCIe 3.1 | 8 | ||||
PCIe 2.1 | 5 |
Feature | PCIe 6.0 Controller | PCIe 5.0 Controller | PCIe 4.0 Controller | PCIe 3.1 Controller | PCIe 2.1 Controller |
---|---|---|---|---|---|
Data Rate (GT/s) | 64 | 32 | 16 | 8 | 5 |
Data Path | Scalable | Scalable | Scalable | Scalable | Scalable |
Topologies Supported | Root Port Endpoint Switch Port Dual-Mode | Root Port Endpoint Switch Port Dual-Mode | Root Port Endpoint Switch Port Dual-Mode | Root Port Endpoint Switch Port Dual-Mode | Root Port Endpoint Switch Port Dual-Mode |
Duplex Lane Configurations | x1, x2, x4, x8, x16 | x1, x2, x4, x8, x16 | x1, x2, x4, x8, x16 | x1, x2, x4, x8, x16 | x1, x2, x4, x8, x16 |
Backward Compatibility | 5.0, 4.0, 3.1/3.0 | 4.0, 3.1/3.0 | 3.1/3.0 | 3.0/2.1/2.0 | 1.1/1.0 |
Clock Gating/Power Gating | Yes | ||||
Advanced RAS | Yes | Yes | Yes | Yes | Yes |
Virtual Channel Support | FLIT and non-FLIT mode | ||||
Forward Error Correction (FEC) | Yes | ||||
L0p Low Power Mode | Yes | ||||
Optional Features | IDE Security, AER, ECRC, ECC, MSI, MSI-X, Multifunction, Crosslink | AER, ECRC, ECC, MSI, MSI-X, Multifunction, Crosslink | AER, ECRC, ECC, MSI, MSI-X, Multifunction, Crosslink | AER, ECRC, ECC, MSI, MSI-X, Multifunction, Crosslink | AER, ECRC, ECC, MSI, MSI-X, Multifunction, Crosslink P2P |
Feature | PCIe 6.0 PHY | PCIe 5.0 PHY | PCIe 4.0 PHY |
---|---|---|---|
Data Rate (GT/s) | Up to 64 | Up to 32 | Up to 16 |
Controller Interface | PIPE 6.0 | PIPE 5.1 | PIPE 4.2 |
Backward Compatibility | 5.0, 4.0, 3.1/3.0 | 4.0, 3.1/3.0, 2.1/2.0 | 3.1/3.0, 2.1/2.0 |
CXL Support | 3.0, 2.0, 1.1 | 2.0, 1.1 | |
Duplex Lane Configurations | x1, x2, x4, x8, x16 | x1, x2, x4, x8, x16 | x2, x4, x8 |
Multi-tap Tx Finite Impulse Response (FIR) Equalizer with Multi-level De-emphasis | Yes | Yes | Yes |
Compensation for >36dB Channel Insertion Loss Across PVT | Yes | Yes | Yes |
Tx/Rx Spread Spectrum Clocking for EMI | Yes | Yes | |
Built-in Self-Test with ATPG and AC/DC Boundary Scan | Yes | Yes | Yes |
Built-in PRBS | Yes | Yes | Yes |
In-situ Real-time Monitoring and Receive Data Eye Schmoo | Yes | Yes | Yes |
Automatic Calibration of Key Circuits | Yes | Yes | Yes |
LabStation™ Software Environment for System Level Bring-up, Characterization, and Validation | Yes | Yes | Yes |
Solution | Product Brief | Description |
---|---|---|
PCIe 6.0 Retimer Controller | PCIe 6.0 Retimer Controller with CXL Support Provides Highly Optimized, Low-latency Data Path for Signal Regeneration | |
PCIe 5.0 Multi-port Switch | Customizable Multi-port Switch, Connects One Upstream Port to Up to 31 Downstream Ports | |
PCIe Controller for USB4 | PCIe 5 Controller with USB4 Support, with Native Logic Interface Options | |
PCIe Controller for USB4 with AXI | PCIe 5 Controller with USB4 Support, with AXI Logic Interface Options | |
PCIe Switch for USB4 | Customizable Switch with USB4 Support, Connects One Upstream Port to Up to 31 Downstream Ports | |
Many-Channel AXI DMA | Highly-efficient, Configurable DMA Engine Supports Distribution of Hundreds of DMA Channels Across VMs or Hosts |
Solution | Product Brief | Description |
---|---|---|
INSPECTOR for PCIe 5.0 | Interposer Card for Diagnostic Testing, Exercising and Debug of PCIe Devices at up to 32 GT/s | |
Gen5HOST | Host Enabling Reference Platform for Prototyping and Development of PCIe 5.0 Devices and Apps | |
Gen5ENDPOINT | Endpoint Reference Platform for Prototyping and Development of PCIe 5.0 Devices | |
XpressAGENT | Add-on Core Simplifies Observability and Expedites Debugging of PCIe and CXL subsystems |
The Rambus PCIe 6.0 Controller exposes a highly efficient transmit (Tx) and receive (Rx) interface with configurable bus widths. Designed to satisfy a multitude of customer and industry use cases, the IP can be configured to support endpoint, root port, switch port, and dual-mode topologies, allowing for a variety of use models. The provided Graphical User Interface (GUI) Wizard allows designers to tailor the IP to their exact requirements, by enabling, disabling, and adjusting a vast array of parameters.
The Rambus 6.0 PHY IP consists of a Physical Media Attachment (PMA) designed with a minimal set of broadside controls and status pins to support a wide range of server, storage and networking applications. The PHY can be combined with the Rambus PCIe 6.0 digital controller to offer a fully integrated and validated interface subsystem.
The PCIe interface is the critical backbone that moves data at high bandwidth and low latency between various compute nodes such as CPUs, GPUs, FPGAs, and workload-specific accelerators. With the torrid rise in bandwidth demands of advanced workloads such as AI/ML training, PCIe 6.0 jumps signaling to 64 GT/s with some of the biggest changes yet in the standard.