PCI Express Interconnect Subsystem IP

Delivering high-bandwidth interconnect performance

PCI Express Controller and PHY IP

Rambus silicon-proven, high-performance PCI Express® (PCIe®) 6.0, 5.0, 4.0 and earlier generation digital controllers, PHYs and complete interconnect subsystems are optimized for use in SoCs, ASICs and FPGAs. These market-leading solutions for high-performance interfaces address AI/ML, data center and edge applications.

PCIe Controller IP

FeaturePCIe 6.0
Controller
PCIe 5.0
Controller
PCIe 4.0
Controller
PCIe 3.1
Controller
PCIe 2.1
Controller
Data Rate (GT/s)64321685
Data PathScalableScalableScalableScalableScalable
Topologies SupportedRoot Port
Endpoint
Switch Port
Dual-Mode
Root Port
Endpoint
Switch Port
Dual-Mode
Root Port
Endpoint
Switch Port
Dual-Mode
Root Port
Endpoint
Switch Port
Dual-Mode
Root Port
Endpoint
Switch Port
Dual-Mode
Duplex Lane Configurationsx1, x2, x4, x8, x16x1, x2, x4, x8, x16x1, x2, x4, x8, x16x1, x2, x4, x8, x16x1, x2, x4, x8, x16
Backward Compatibility5.0, 4.0, 3.1/3.04.0, 3.1/3.03.1/3.03.0/2.1/2.01.1/1.0
Clock Gating/Power GatingYes    
Advanced RASYesYesYesYesYes
Virtual Channel SupportFLIT and non-FLIT mode    
Forward Error Correction (FEC)Yes    
L0p Low Power ModeYes    
Optional FeaturesIDE Security,
AER,
ECRC,
ECC,
MSI,
MSI-X,
Multifunction,
Crosslink
AER,
ECRC,
ECC,
MSI,
MSI-X,
Multifunction,
Crosslink
AER,
ECRC,
ECC,
MSI,
MSI-X,
Multifunction,
Crosslink
AER,
ECRC,
ECC,
MSI,
MSI-X,
Multifunction,
Crosslink
AER,
ECRC,
ECC,
MSI,
MSI-X,
Multifunction,
Crosslink
P2P

PCIe PHY IP

FeaturePCIe 6.0 PHYPCIe 5.0 PHYPCIe 4.0 PHY
Data Rate (GT/s)Up to 64Up to 32Up to 16
Controller InterfacePIPE 6.0PIPE 5.1PIPE 4.2
Backward Compatibility5.0, 4.0, 3.1/3.04.0, 3.1/3.0, 2.1/2.03.1/3.0, 2.1/2.0
CXL Support3.0, 2.0, 1.12.0, 1.1 
Duplex Lane Configurationsx1, x2, x4, x8, x16x1, x2, x4, x8, x16x2, x4, x8
Multi-tap Tx Finite Impulse Response (FIR) Equalizer with Multi-level De-emphasisYesYesYes
Compensation for >36dB Channel Insertion Loss Across PVTYesYesYes
Tx/Rx Spread Spectrum Clocking for EMIYesYes 
Built-in Self-Test with ATPG and AC/DC Boundary ScanYesYesYes
Built-in PRBSYesYesYes
In-situ Real-time Monitoring and Receive Data Eye SchmooYesYesYes
Automatic Calibration of Key CircuitsYesYesYes
LabStation™ Software Environment for System Level Bring-up, Characterization, and ValidationYesYesYes

PCIe Switch, Retimer, DMA and USB4 IP

Solution Product Brief Description
PCIe 6.0 Retimer Controller Download PCIe 6.0 Retimer Controller Product Brief PCIe 6.0 Retimer Controller with CXL Support Provides Highly Optimized, Low-latency Data Path for Signal Regeneration
PCIe 5.0 Multi-port Switch Download PCIe 5.0 Multi-port Switch Product Brief Customizable Multi-port Switch, Connects One Upstream Port to Up to 31 Downstream Ports
PCIe Controller for USB4 Download PCIe Controller for USB4 Product Brief PCIe 5 Controller with USB4 Support, with Native Logic Interface Options
PCIe Controller for USB4 with AXI Download PCIe Controller for USB4 with AXI Product Brief PCIe 5 Controller with USB4 Support, with AXI Logic Interface Options
PCIe Switch for USB4 Download PCIe Switch for USB4 Product Brief Customizable Switch with USB4 Support, Connects One Upstream Port to Up to 31 Downstream Ports
Many-Channel AXI DMA Download Many-Channel AXI DMA Product Brief Highly-efficient, Configurable DMA Engine Supports Distribution of Hundreds of DMA Channels Across VMs or Hosts

PCIe Debug and Test Solutions, and Add-On Cores

SolutionProduct BriefDescription
INSPECTOR for PCIe 5.0Download INSPECTOR for PCIe 5.0 Product Brief Interposer Card for Diagnostic Testing, Exercising and Debug of PCIe Devices at up to 32 GT/s
Gen5HOSTDownload the Gen5HOST Product Brief Host Enabling Reference Platform for Prototyping and Development of PCIe 5.0 Devices and Apps
Gen5ENDPOINTDownload the Gen5ENDPOINT Product Brief Endpoint Reference Platform for Prototyping and Development of PCIe 5.0 Devices
XpressAGENTDownload the XpressAGENT Product Brief Add-on Core Simplifies Observability and Expedites Debugging of PCIe and CXL subsystems

Complete PCIe 6.0 Interconnect Subsystem Solution

The Rambus PCIe 6.0 Controller exposes a highly efficient transmit (Tx) and receive (Rx) interface with configurable bus widths. Designed to satisfy a multitude of customer and industry use cases, the IP can be configured to support endpoint, root port, switch port, and dual-mode topologies, allowing for a variety of use models. The provided Graphical User Interface (GUI) Wizard allows designers to tailor the IP to their exact requirements, by enabling, disabling, and adjusting a vast array of parameters.

PCIe 6.0 Interface Subsystem Solution
PCIe 6.0 Interface Subsystem Solution

The Rambus 6.0 PHY IP consists of a Physical Media Attachment (PMA) designed with a minimal set of broadside controls and status pins to support a wide range of server, storage and networking applications. The PHY can be combined with the Rambus PCIe 6.0 digital controller to offer a fully integrated and validated interface subsystem.

Data Center Evolution: The Leap to 64 GT/s Signaling with PCI Express 6.0

Data Center Evolution: The Leap to 64 GT/s Signaling with PCI Express 6.0

The PCIe interface is the critical backbone that moves data at high bandwidth and low latency between various compute nodes such as CPUs, GPUs, FPGAs, and workload-specific accelerators. With the torrid rise in bandwidth demands of advanced workloads such as AI/ML training, PCIe 6.0 jumps signaling to 64 GT/s with some of the biggest changes yet in the standard. 

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