Rambus

At Rambus, we create cutting-edge semiconductor and IP products, spanning memory and interfaces to security, smart sensors and lighting.

PCIe 5.0 Controller

Contact Us

The Rambus PCIe 5.0 Controller (formerly XpressRICH from PLDA) is designed to achieve maximum PCI Express (PCIe) 5.0 performance with great design flexibility and ease of integration. It is fully backward compatible with PCIe 4.0 and 3.1/3.0. A PCIe 5.0 Controller with AXI (formerly XpressRICH-AXI) is also available. The controller with the Rambus PCIe 5.0 PHY forms a comprehensive interface subsystem solution delivering high-bandwidth and low-latency connectivity for next-generation applications in artificial intelligence/machine learning (AI/ML), data center, edge, 5G infrastructure and graphics.

Contact Us IconContact
Product Briefs
PCIe 5.0 Controller Product BriefPCIe 5.0 Controller
PCIe 5.0 Controller with AXI Product BriefPCIe 5.0 Controller with AXI
PCIe 5.0 Interface Subsystem Product BriefPCIe 5.0 Interface Subsystem

How the PCIe 5.0 Controller Works

The PCIe 5.0 Controller is configurable and scalable IP designed for ASIC and FPGA implementation. It supports the PCIe 5.0, 4.0 and 3.1/3.0 specifications, as well as the version 5.x of the PHY Interface for PCI Express (PIPE) specification. The IP can be configured to support endpoint, root port, switch port, and dual-mode topologies, allowing for a variety of use models.

PCIe 5.0 Controller Block Diagram
PCIe 5.0 Controller Block Diagram
PCIe 5.0 Controller with AXI Block Diagram
PCIe 5.0 Controller with AXI Block Diagram
PCIe 5.0 Interface Subsystem solution
PCIe 5.0 Interface Subsystem Solution

The Rambus PCIe 5.0 PHY and PCIe 5.0 Controller comprise a complete PCIe 5.0 interface subsystem. The PCIe 5 SerDes PHY is available on an advanced 7nm FinFET process node. The PCIe 5.0 controller can be synthesized on any process.

Data Center Evolution: The Leap to 64 GT/s Signaling with PCI Express 6.0

Data Center Evolution: The Leap to 64 GT/s Signaling with PCI Express 6.0

The PCIe interface is the critical backbone that moves data at high bandwidth and low latency between various compute nodes such as CPUs, GPUs, FPGAs, and workload-specific accelerators. With the torrid rise in bandwidth demands of advanced workloads such as AI/ML training, PCIe 6.0 jumps signaling to 64 GT/s with some of the biggest changes yet in the standard.
Download White Paper

Solution Offerings

Protocol Compatibility

Protocol Signaling Rate (GT/s) Application
PCIe 3.1/3.0 8 Servers, storage, networking devices
PCIe 4.0 16 Servers, storage, networking devices
PCIe 5.0 32 AI, servers, storage, networking, 5G infrastructure
SerDes Signal Integrity Challenges at 28Gbps and Beyond

SerDes Signal Integrity Challenges at 28Gbps and Beyond

Maintaining signal integrity has become increasingly difficult as data rates moves past 28Gbps to 56Gbps and beyond. Up to 28Gbps rates, NRZ is the preferred and standardized encoding scheme which consists of 1’s and 0’s. NRZ is also referred to as PAM2 (pulse amplitude modulation, 2-level), due to its two amplitude levels which contain 1 bit of information in every symbol. With serial data rates hitting 56 Gb/s per channel, signal impairments caused by increased bandwidth has prompted the high-speed serial data industry to adopt PAM4, or 4-level pulse amplitude modulation.
Download White Paper

Inventions

Phase Interpolator-Based CDR

Reduces cost, power and area of clock and data recovery (CDR) circuit and improves jitter performance in high-speed parallel and serial links versus PLL-based CDRs.

From the blog

Resources

News

Related Papers

Webinars

Related Markets & Applications

Data Center
Rambus logo