DDR Memory Interface Subsystem IP

Delivering high-bandwidth memory performance

DDR Memory Controller and PHY IP

Rambus DDR4 and DDR3 Controller, PHY and memory interface subsystems deliver high-bandwidth, and power efficiency while providing full compatibility with the DDR4 and DDR3 industry standards.
VersionMaximum Data Rate (MT/s)ControllerPHY
DDR43200Download DDR4 Controller Product Brief Product BriefDownload DDR4 PHY Product Brief Product Brief
DDR4 Multi-modal*2400Download DDR4 Controller Product Brief Product BriefDownload DDR4 Multi-modal Product Brief Product Brief
DDR32133Download DDR3 Controller Product Brief Product BriefDownload DDR3 Multi-modal Product Brief Product Brief

*Supports DDR4, DDR3, LPDDR3 and LPDDR2

DDR Controller IP

FeatureDDR4 ControllerDDR3 Controller
Data Rate (MT/s)1600 to 3200800 to 2133
Clock OperationHalf-rate and quarter-rateFull-rate and half-rate
Bank ManagementUp to 32 banksUp to 32 banks
SDRAM Feature Support3DS device configurations
Write CRC
Data bus inversion (DBI)
Fine granularity refresh
Additive latency
Per-DRAM addressability
Temperature-controlled refresh
Dynamic ODT
2T timing
Write leveling calibration
Interface to LogicNative or AXINative or AXI
DFI CompatibleYesYes
Multi-mode Controller SupportYesYes
Add-On CoresMulti-Port Front-End
Multi-Port Front-End


Feature DDR4 PHY DDR4 Multi-modal PHY DDR3 PHY
Data Rate (MT/s) Up to 3200 Up to 2400 Up to 2133
Controller Interface DFI 4.0 and 3.1 DFI 3.1 DFI 3.1
Autonomous initialization (PHY independent mode) Yes Yes Yes
Channel width x16 to x72 x4 to x32 x16 to x72
Selectable low-power operating states Yes Yes Yes
Programmable output impedance and on-die termination Yes Yes Yes
ZQ calibration of output impedance and on-die termination Yes Yes Yes
Package options Package-on-package and C4 flip-chip Package-on-package and C4 flip-chip C4 flip-chip
Metal stack 8 or 13 layer 8 layer 8 layer
Register interface for state observation Yes Yes Yes
Test traffic generation and error checking in-situ test Yes Yes
LabStation™ software environment for system level bring-up, characterization, and validation Yes Yes Yes
On-chip Power Supply Noise Monitor optional add-on core Yes Yes Yes

Complete DDR4 Memory Subsystem Solution

The Rambus DDR4 memory subsystem delivers industry-leading data rates of up to 3200 Mbps and is compatible with the DDR4 and DDR3 standards. The PHY consists of a Command/Address (C/A) macro cell and Data (DQ) macro cells configured to create a 72-bit wide channel.

The Rambus DDR4 controller maximizes memory bus efficiency via Look-Ahead command processing, bank management, auto-precharge and additive latency support. The core is DFI compatible and supports a range of interfaces to user logic.

DDR4 Memory Interface Subsystem
DDR4 Memory Interface Subsystem

The Rambus DDR4 controller and PHY used together comprise a complete DDR4 memory interface subsystem. Alternatively, these cores can be licensed separately to be paired with 3rd-party DDR4 controller or PHY solutions.

Rambus logo