At Rambus, we create cutting-edge semiconductor and IP products, spanning memory and interfaces to security, smart sensors and lighting.
DDR Memory Controller and PHY IP
| Version | Maximum Data Rate (MT/s) | Controller | PHY |
|---|---|---|---|
| DDR4 | 3200 |  Product Brief | Product Brief |
| DDR4 Multi-modal* | 2400 | Product Brief | Product Brief |
| DDR3 | 2133 | Product Brief | Product Brief |
*Supports DDR4, DDR3, LPDDR3 and LPDDR2
DDR Controller IP
| Feature | DDR4 Controller | DDR3 Controller |
|---|---|---|
| Data Rate (MT/s) | 1600 to 3200 | 800 to 2133 |
| Clock Operation | Half-rate and quarter-rate | Full-rate and half-rate |
| Bank Management | Up to 32 banks | Up to 32 banks |
| SDRAM Feature Support | 3DS device configurations Write CRC Data bus inversion (DBI) Fine granularity refresh Additive latency Per-DRAM addressability Temperature-controlled refresh | ODT Dynamic ODT 2T timing Write leveling calibration |
| Interface to Logic | Native or AXI | Native or AXI |
| DFI Compatible | Yes | Yes |
| Multi-mode Controller Support | Yes | Yes |
| Add-On Cores | Multi-Port Front-End Reorder ECC | Multi-Port Front-End Reorder ECC |
DDR PHY IP
| Feature | DDR4 PHY | DDR4 Multi-modal PHY | DDR3 PHY |
|---|---|---|---|
| Data Rate (MT/s) | Up to 3200 | Up to 2400 | Up to 2133 |
| Controller Interface | DFI 4.0 and 3.1 | DFI 3.1 | DFI 3.1 |
| Autonomous initialization (PHY independent mode) | Yes | Yes | Yes |
| Channel width | x16 to x72 | x4 to x32 | x16 to x72 |
| Selectable low-power operating states | Yes | Yes | Yes |
| Programmable output impedance and on-die termination | Yes | Yes | Yes |
| ZQ calibration of output impedance and on-die termination | Yes | Yes | Yes |
| Package options | Package-on-package and C4 flip-chip | Package-on-package and C4 flip-chip | C4 flip-chip |
| Metal stack | 8 or 13 layer | 8 layer | 8 layer |
| Register interface for state observation | Yes | Yes | Yes |
| Test traffic generation and error checking in-situ test | – | Yes | Yes |
| LabStation™ software environment for system level bring-up, characterization, and validation | Yes | Yes | Yes |
| On-chip Power Supply Noise Monitor optional add-on core | Yes | Yes | Yes |
Complete DDR4 Memory Subsystem Solution
The Rambus DDR4 memory subsystem delivers industry-leading data rates of up to 3200 Mbps and is compatible with the DDR4 and DDR3 standards. The PHY consists of a Command/Address (C/A) macro cell and Data (DQ) macro cells configured to create a 72-bit wide channel.
The Rambus DDR4 controller maximizes memory bus efficiency via Look-Ahead command processing, bank management, auto-precharge and additive latency support. The core is DFI compatible and supports a range of interfaces to user logic.
The Rambus DDR4 controller and PHY used together comprise a complete DDR4 memory interface subsystem. Alternatively, these cores can be licensed separately to be paired with 3rd-party DDR4 controller or PHY solutions.
- Controller (source code)
- Testbench (source code)
- Complete documentation
PHY
Fully-characterized hard macro (GDSII)
- Complete design views:
- Gate-level and IO models
- Verification test benches
- Layout abstracts (.lef)
- Timing models (.lib)
- Full documentation:
- Datasheet
- Package and interposer design guidelines
- ASIC/DFT manufacturing guidelines
- Test and characterization user guide
- Verilog models
- CDL netlists (.cdl)
- GDSII layout
- DRC & LVS reports
- Expert technical support
- Maintenance updates
- Customization
- SoC Integration
PHY
Comprehensive Chip and System Design Reviews
- Kickoff/Program Review
- Floor plan Review
- Test/Characterization Plan Review
- Package Design Review
- Board Design Review
- Final Chip Integration Review
- Bring-up and Test Review
Engineering Design Services:
- Package design
- System board layout
- Statistically-based signal and power integrity analysis
