Explore innovations that enable the superior performance of Rambus solutions

32X Data Rate Transfers 32 bits of data per I/O on each clock cycle – 16 times as many data bits as the DDR (double data rate) techniques common in many DRAM products today. 32X Data Rate was developed through the Rambus
Advanced Power State Management Advanced power states in a memory system that enable and disable critical circuitry, such as input receivers and clock circuits, provide an effective way to lower memory system power for various system performance levels.
Asymmetric Equalization Enables very high bandwidth on next generation memory systems. Signal equalization is applied asymmetrically across the memory PHY and DRAM communication link and improves overall signal integrity while minimizing the complexity and cost of the DRAM device.
Binary Operation Binary operation enables the imagers to sense photons using discrete thresholds, similar to the human eye, for better sensitivity across the gamut of dark to bright and improved dynamic range.
Buffered Modules As memory systems continue to evolve, memory system bandwidth is advancing to higher levels through the use of wider memory system buses and faster per-pin signaling rates.
Channel Equalization Improves receive eye and system margins by reducing Inter-Symbol Interference (ISI) in high speed parallel and serial link channels.
Clock Multiplying DLL Improves integration levels and noise rejection capability for high speed parallel and serial links.
Clocked DDR Address/Control Sending address and control information with a double data-rate signals improves memory performance efficiency and enables higher effective bandwidth.
Color Temperature Change Cost-effectively enables in-lamp color temperature change from warm to neutral to cool with the turn of a dial through the use of an adjustable remote phosphor and a color mixing light guide.
Core Prefetch Improves interface bandwidth while allowing the core to operate at a lower frequency.
Differential Rambus Signaling Levels (DRSL) A low-voltage, low-power, differential signaling standard that enables the scalable multi-GHz, bi-directional, and point-to-point data busses that connect the XIO™ cell to XDR™ DRAM devices.
Digital CDR with Fast Recovery Enables fast recovery with low-latency from a low-power state.
DLL/PLL on a DRAM Improves maximum operating frequency of a memory system by optimizing Input/Output (IO) timing.
Double Bus Rate Technology Doubles the transfer rate out of a memory core without the need for higher system clock speeds.
DPA Countermeasures Fundamental techniques to protect against side-channel attacks including a broad range of hardware, software and protocol techniques to secure tamper resistant devices
Dual Loop PLL/DLL Reduces power, silicon area, and cost of an integrated circuit using a PLL/DLL. Allows a PLL/DLL to lock to several arbitrary phases while sharing critical common circuitry.
Dynamic Point-to-Point Enables memory upgrades and expandable capacity while maintaining high-performance point-to-point signaling.
Dynamic Point-to-Point Technology Enhanced Enables the performance, scalability and capacity needs of next generation memory systems. DPP supports FlexLink™ C/A allowing dynamic point-to-point capability for command/address signals. DPP enables the scaling of memory system capacity and access granularity.
Enhanced FlexPhase™ Timing Adjustments Enables flexible phase relationships between signals, allowing precise on-chip alignment of data with command/address and clock. FlexPhase enhancements improve the sensitivity and capability of FlexPhase circuits for very high performance memory systems operating at data rates of up to 20Gbps. Enhanced FlexPhase technology was developed through the Rambus Terabyte Bandwidth Initiative.
FlexClocking™ Architecture FlexClocking technology is an architecture that utilizes asymmetric partitioning and places critical calibration and timing circuitry in the controller interface, greatly simplifying the design of the DRAM interface.
FlexLink™ C/A Interface Industry’s first full-speed, scalable point-to-point command/address channel. FlexLink C/A provides the command and address information to a DRAM using a single, differential high speed communications channel. FlexLink C/A was developed through the Rambus Terabyte Bandwidth Initiative.
FlexMode™ Interface Enables support of differential and single-ended memory interfaces in a single SoC package design, with no additional pins, through programmable assignment of signaling IOs as either data or command/address.
FlexPhase™ Timing Adjustment Circuits Enables flexible phase relationships between signals, allowing precise on-chip alignment of data with clock. FlexPhase technology is a key technology ingredient for achieving high data rates on chip-to-chip systems that reference an external clock signal. In addition, FlexPhase timing adjustments, which can be particularly beneficial in Fly-by architecture, eliminate many timing offsets associated with process variations, driver/receiver mismatch, on-chip clock skew and clock standing wave effects. FlexPhase technology’s automatic centering of data and clock offers designers a quick and easy design solution for high-speed chip interconnections.
Fly-by Command Address Fly-by command/address architectures improve signal integrity in memory systems, thus enabling higher per-pin bit rates and systems capable of GHz data rates. When used in combination with FlexPhase™ circuits that deskew the timing of source synchronous signals, the Fly-by command/address architecture increases memory bandwidth, maintains low latency, and avoids the need for clock-encoding. Fly-by architectures have been used in Rambus memory systems to enable scalability without compromising data rates.
Fully Differential Memory Architecture Industry’s first memory architecture that incorporates differential signaling technology on all key signal connections between the memory controller and the DRAM. Fully Differential Memory Architecture (FDMA) enables higher speed, lower noise and lower power in high performance memory systems. FDMA was developed through the Rambus Terabyte Bandwidth Initiative.
Jitter Reduction Technology Improves the signal integrity of very high speed communications links. By reducing jitter, memory signaling performance of 16Gbps can be achieved, enabling the terabyte bandwidth performance levels of next generation memory systems.
Micro-Threading Technology Reduce row and column access granularity resulting in a significant performance benefit for applications dealing with small data objects.
MicroLens® Optics Light distribution features that provide customizable control of uniformity and ray angle for superior application efficiency.
Module Connector Compensation Improves operating frequency of systems utilizing module connectors by mitigating the impedance discontinuity of the electrical interconnection.
Module Impedance Compensation Improves operating frequency of a module by mitigating the discontinuity caused by soldered-on device loading.
Module Threading Module Threading improves the throughput and power efficiency of a memory module by applying parallelism to module data accesses.
Multi-Level Signaling Applied to Backplanes Improves data rates and systems margins in high-speed parallel and serial links used in frequency limited channels.
Near Ground Signaling Near Ground Signaling (NGS) is a single-ended, ground-terminated signaling technology that enables high data rates at significantly reduced IO signaling power and design complexity, while maintaining excellent signal integrity.
On Die Termination Calibration Incorporates On Die Termination impedance improving the signaling environment by reducing the electrical discontinuities introduced with off-die termination.
Output Driver Calibration Improves data rates and system voltage margin by maintaining stable current or voltage drive levels referenced to a precision external resistor.
Phase Interpolator-Based CDR Reduces cost, power, and area of a clock and data recovery circuit, and improves jitter performance in high-speed parallel and serial links versus PLL clock and data recovery (CDRs).
SolidCore™ Reflectors Compact reflectors capable of producing tightly controlled, efficient and high-intensity beams ideal for spotlights.
Spatial Oversampling Spatial oversampling sub-divides Individual pixels to capture more data and extend dynamic range of the imager.
System Flight Time Levelization Enables very large capacity bussed memory or logic systems which operate at high frequency. Simplifies read/write scheduling from the controller logic.
Temperature Compensated Self-Refresh Enables lower memory power during self-refresh by compensating the refresh rate based on temperature.
TruEdge™ LED Coupling LED-to-light guide coupling technology that delivers 93 to 96 % of total LED output to the light guide.
Variable Temporal Oversampling Variable temporal oversampling takes multiple samples during a single exposure period to avoid pixel saturation improving the sensor’s signal-to-noise ratio and low-light performance for better indoor and nighttime photography.
Very Low-Swing Differential Signaling Very Low-Swing Differential Signaling (VLSD) is a bi-directional, ground-referenced, differential signaling technology which offers a high-performance, low-power, and cost-effective solution for applications requiring extraordinary bandwidth and superior power efficiency.
VirtuOptic™ Reflectors Produce a highly collimated, highly efficient light output while delivering precise ray angle control.
Wide Frequency Range PLL Simplifies parallel and serial link applications with continuous, wide-range frequency adjustment capability.