In memory architectures, it can be used to deskew data bits inbound to the controller (Reads) in order to compensate for uncertainty in the arrival times of signals. Enhanced FlexPhase™ circuits implemented in a memory controller finely tune the timing relationships between data, command and address (C/A), and clock signals to eliminate the need for trace length matching in systems operating up to 20Gbps. Further, Enhanced FlexPhase circuits can inject a timing offset, or “preskew,” such that the data outbound from the controller (Writes) arrives at the DRAM devices coincident with the C/A signals.
- Eliminates trace length matching on system boards and memory devices packaging at speeds up to 20Gbps
- Reduces board and packaging costs
- Enables timing calibration at extremely high signaling rates
What is Enhanced FlexPhase Technology?
Enhanced FlexPhase technology anticipates the phase difference between signals on separate traces and manages the transmission of bits so that data arrives with a known timing relationship with respect to the C/A signal. It can also adjust for differences in signal propagation times due to manufacturing variations in trace lengths. Building on the foundation of FlexPhase technology, Enhanced FlexPhase technology adds:
- New circuit innovations to increase phase linearity and tighten timing resolutions to support data rates of up to 20Gbps
- Innovative timing calibration algorithms for optimizing phase settings of C/A signals at initialization and in active operation
- Methods to statistically measure bit error rate (BER) at low enough magnitudes to account for all deterministic jitter (DJ) sources
- Ability to measure BER during characterization of the memory system
Enhanced FlexPhase circuits include in-system timing characterization and self-test functionality that enables extremely fine timing resolutions in high-performance memory systems. Enhanced FlexPhase technology incorporates calibration algorithms that establish communication of the C/A signal and accelerate the search for the optimal phase value. In active operation, Enhanced FlexPhase circuits can also periodically fine-tune the timing of the C/A signals without disturbing the operational state of the DRAMs.
Enhanced FlexPhase technology eliminates the need to match trace lengths both on system circuit boards and within memory device packages. Such system simplification allows greater flexibility and lowers board and packaging costs. It also improves overall system timing through dynamic compensation for process variations, on-chip clock skew, driver/receiver mismatch and clock standing wave effects. Enhanced FlexPhase technology delivers these system benefits even at extremely high signaling rates up to 20Gbps.