Memory + Interfaces

>>Memory + Interfaces

Phase Interpolator-Based CDR

In order to communicate data from one chip to another across a signal line, the receiving chip must know when to sample the data signal that it receives from the transmitting chip. In many systems, this information is provided by a timing (clock) signal sent from the transmitting chip to the receiving chip along a [...]

Output Driver Calibration

Transmitting data at high speeds between a DRAM device and a memory controller requires careful design of IO drivers to ensure that the required electrical signaling levels are achieved. Variations in process, voltage, and temperature can alter the electrical characteristics of the output driver circuitry, resulting in deviations from the desired signaling levels. Additionally, variations [...]

Near Ground Signaling

Reduced power consumption has become of key importance in memory system design—from mobile to enterprise-class applications. In addition to clocking power and DRAM core access power, IO signaling power must be addressed in order to reduce the total power consumption of the memory system. Near ground signaling is a single-ended, ground-terminated technology theat enables high [...]

Module Threading

The growing trend of multi-core processing and converged graphics-compute processors is increasing the performance requirements on the DRAM memory subsystems. Multi-thread computing and graphics not only need higher memory bandwidth but also generate more random accesses to smaller pieces of data. Module Threading improves the throughput and power efficiency of a memory module by applying [...]

FlexPhase™ Timing Adjustment Circuits

Precise on-chip alignment of data clock are crucial for today’s high performance memory systems. In addition, offsets in timing caused by variations in process, voltage and timing must be accounted for. FlexPhase™ Timing Adjustment Circuits are a key technology ingredient for achieving high data rates on chip-to-chip systems that reference an external clock signal. By [...]

Double Bus Rate Technology

In many computing systems today, memory bandwidth is a key factor in determining overall system performance, and its importance continues to grow as these systems evolve. Rambus developed a technique for improving memory system bandwidth by increasing the per-pin signaling rate of the data pins of the DRAM. Double Data Rate (DDR) SDRAMs are an [...]

Asymmetric Equalization

Enables very high bandwidth on next generation memory systems. Signal equalization is applied asymmetrically across the memory PHY and DRAM communication link and improves overall signal integrity while minimizing the complexity and cost of the DRAM device. […]

Very Low-Swing Differential Signaling

Today’s mobile device demand high bandwidth for HD video capture and streaming, and media-rich web browsing as well as extended battery life. Very Low-Swing Differential Signaling (VLSD) is a bi-directional, ground-referenced, differential signaling technology which offers a high-performance, low-power, and cost-effective solution for applications requiring extraordinary bandwidth and superior power efficiency. Enables high data rates [...]

On Die Termination Calibration

As the performance requirements of digital systems continue to increase, there are increasing requirements to deliver signal integrity that enables reliable operation at higher signaling rates. Signal line terminations are useful elements in the management of signal integrity, and can be use external to the memory device or within the device itself. Incorporating a resistive [...]

Micro-Threading Technology

Improvements in DRAM interface throughput have rapidly outpaced comparable improvements in core speeds. Whereas data rates of DRAM interfaces have increased by over an order of magnitude over successive generations, the DRAM core frequency has remained relatively constant. Over time, core prefetch size has increased in order to keep pace with improvements in interface bandwidth. [...]