At Rambus, we create cutting-edge semiconductor and IP products, spanning memory and interfaces to security, smart sensors and lighting.
GDDR Memory Controller and PHY IP
Rambus GDDR6 controllers, PHYs and memory interface subsystems provide high-bandwidth, low-latency memory performance for AI/ML, graphics and HPC applications.
| Version | Maximum Data Rate (Gb/s) | Subsystem | Controller | PHY |
|---|---|---|---|---|
| GDDR6 | 24 |  Product Brief |
Product Brief |
Product Brief |
| GDDR6 | 16 | Product Brief |
Product Brief |
Product Brief |
GDDR Controller IP
| Feature | GDDR6 Controller |
|---|---|
| Speed Per Pin (Gb/s) | Up to 24 |
| Channels | 2 |
| Channel Width (bits) | 16 |
| Queue-Based Interface | Yes |
| Look-Ahead Command Processing | Yes |
| Clamshell Mode | x8 and x16 |
| Logic Interface | AXI or Native |
| Controller Interface | DFI Compatible |
| Add-On Cores | In-line ECC Multi-Port Front-End Reorder Read-Modify-Write Memory Test Memory Test Analyzer |
GDDR PHY IP
| Feature | 24G GDDR6 PHY | 16G GDDR6 PHY |
|---|---|---|
| Speed Bins (Gb/s) | 14-24 | 12-16 |
| Maximum Bandwidth (GB/s) | 96 | 64 |
| Channels | 2 | 2 |
| Channel Width (bits) | 16 | 16 |
| Controller Interface | DFI 3.1 Style | DFI 3.1 Style |
| PHY Independent Mode | Yes | Yes |
| Clamshell Mode | Yes | Yes |
| Selectable low-power operating states | Yes | Yes |
| Programmable driver/termination impedance | Yes | Yes |
| In-built test support | Yes | Yes |
| Metal stack | 15 layers | 13 layers |
| Bump pitch (um) | 110 | 130 |
| Integrated Reorder functionality | Yes | Yes |
| Register interface for state observation | Yes | Yes |
| LabStation™ software environment for system level bring-up, characterization, and validation | Yes | |
| Process Node | Contact Rambus | 7nm |
Complete GDDR6 Memory Subsystem Solution
Originally designed for graphics applications, GDDR is a high-performance memory solution that can be used in a variety of compute-intensive applications.
The Rambus GDDR6 controller fully supports the bandwidth and dual channel capabilities of the Rambus GDDR6 PHY. It maximizes memory bandwidth and minimizes latency via Look-Ahead command processing. The core is DFI compatible (with extensions for GDDR6) and supports AXI or native interface to user logic.
Originally designed for graphics applications, GDDR is a high-performance memory solution that can be used in a variety of compute-intensive applications.
The Rambus GDDR6 controller fully supports the bandwidth and dual channel capabilities of the Rambus GDDR6 PHY. It maximizes memory bandwidth and minimizes latency via Look-Ahead command processing. The core is DFI compatible (with extensions for GDDR6) and supports AXI or native interface to user logic.
From Data Center to End Device: AI/ML Inferencing with GDDR6
- Controller (source code)
- Testbench (source code)
- Complete documentation
PHY
Fully-characterized hard macro (GDSII)
- Gate-level and IO models
- Verilog behavior model
- Layout abstracts (.lef)
- Timing models (.lib)
- CDL netlists (.cdl)
- GDSII layout
- DRC & LVS reports
- Datasheet
- Package design guidelines
- ASIC/DFT manufacturing guidelines
- Test and characterization user guide
- Expert technical support
- Maintenance updates
- Customization
- SoC Integration
PHY
Comprehensive Chip and System Design Reviews
- Kickoff/Program Review
- Floor plan Review
- Test/Characterization Plan Review
- Package Design Review
- Board Design Review
- Final Chip Integration Review
- Bring-up and Test Review
Engineering Design Services:
- Package design
- System board layout
- Statistically-based signal and power integrity analysis
