At Rambus, we create cutting-edge semiconductor and IP products, spanning memory and interfaces to security, smart sensors and lighting.
GDDR6 Controller
The Rambus GDDR6 controller core is designed for use in applications requiring high memory throughput including graphics, advanced driver assistance systems (ADAS), data center and artificial intelligence (AI). With the Rambus GDDR6 PHY it comprises a complete GDDR6 memory interface subsystem.
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GDDR6 ControllerHow the 24G GDDR6 Memory Interface Subsystem works
Originally designed for graphics applications, GDDR6 is a high-performance memory solution that can be used in a variety of compute-intensive applications.
The GDDR6 controller fully supports the bandwidth and dual channel capabilities of the Rambus GDDR6 PHY. It maximizes memory bandwidth and minimizes latency via Look-Ahead command processing. The core is DFI compatible (with extensions for GDDR6) and supports AXI or native interface to user logic.
The Rambus GDDR6 PHY is fully compliant to the JEDEC GDDR6 (JESD250C) standard, supporting up to 24 Gb/s per pin. The GDDR6 interface supports 2 channels, each with 16 bits for a total data width of 32 bits. At 24 Gb/s per pin, the Rambus GDDR6 PHY offers a bandwidth of 96 GB/s. Rambus works directly with customers to provide full-system signal and power integrity analysis, creating an optimized chip layout. Customers receive a hard macro solution with a full suite of test software for quick turn-on, characterization and debug.
The Rambus GDDR6 PHY and controller used together comprise a complete GDDR6 memory interface subsystem. Alternatively, these cores can be licensed separately to be paired with 3rd-party GDDR6 controller or PHY solutions.
From Data Center to End Device: AI/ML Inference with GDDR6
Created to support 3D gaming on consoles and PCs, GDDR packs performance that makes it an ideal solution for AI/ML inference. As inference migrates from the heart of the data center to the network edge, and ultimately to a broad range of AI-powered IoT devices, GDDR memory’s combination of high bandwidth, low latency, power efficiency and suitability for high-volume applications will be increasingly important.
Solution Offerings
- Supports up to 24 Gb/s per pin operation
- Can handle two x16 GDDR6 channels with one controller or independently with two controllers
- Supports x8 or x16 clamshell mode
- Queue-based interface optimizes performance and throughput
- Maximizes memory bandwidth and minimizes latency via Look-Ahead command processing
- Automatic retry on transactions where EDC error detected
- Full run-time configurable timing parameters and memory settings
- Supports automatic and controller-initiated training
- DFI compatible (with extensions for GDDR6)
- Full set of Add-On cores available including in-line ECC core
- Supports AXI or native interface to user logic
- Delivered fully integrated and verified with target GDDR6 PHY
- Core (source code)
- Testbench (source code)
- Complete documentation
- Expert technical support
- Maintenance updates
Engineering Design Services:
- Customization
- SoC integration
Protocol Compatibility
| Protocol | Data Rate (Gbps) Max. | Application |
|---|---|---|
| GDDR6 | 24 | AI, Data Center, Graphics |
