Home > Interface IP > HBM Memory Interface Subsystem IP
Rambus High-Bandwidth Memory (HBM) 3.0 and 2E/2 controller, PHY and memory interface subsystems provide high-bandwidth, low-latency memory performance for AI/ML, graphics and HPC applications.
Version | Maximum Data Rate (Gb/s) | Subsystem | Controller | PHY |
---|---|---|---|---|
HBM3 | 8.4 | |||
HBM2E/2 | 3.6/2.0 |
Features | HBM3 Product Brief | HBM2E/2 Product Brief |
---|---|---|
Speed Bins (Gb/s) | Up to 8.4 | Up to 3.6/2.0 |
Channel Densities (Gb) | Up to 32 | Up to 24 |
Channels/Pseudo-Channels | 16/32 | 8/16 |
DRAM Stacks | Up to 16 | Up to 12 |
PHY Interface | DFI Style | DFI Style |
PHY Independent Mode | Yes | Yes |
Refresh Management Support | Yes | |
Look-Ahead Command Processing for Minimum Latency | Yes | Yes |
Integrated Reorder Functionality | Yes | Add-on core |
Self-refresh and Power-down Low Power Modes | Yes | Yes |
RAS Features | Yes | Yes |
Built-in Activity Monitor | Yes | Yes |
DFI Compatible | Yes | Yes |
End-to-end Data Parity | Yes | Yes |
Interface to Logic | Native or AXI | Native or AXI |
Features | HBM3 Product Brief | HBM2E/2 Product Brief |
---|---|---|
Speed Bins (Gb/s) | Up to 8.4 | Up to 3.6 |
Channel Densities (Gb) | Up to 32 | Up to 24 |
Channels/Pseudo-Channels | 16/32 | 8/16 |
DRAM Stacks | Up to 16 | Up to 12 |
Controller Interface | DFI Style | DFI Style |
PHY Independent Mode | Yes | Yes |
Selectable Low-Power Operating States | Yes | Yes |
Programmable Output Impedance | Yes | Yes |
Pin Programmable Support for Lane Repair | Yes | Yes |
ZQ Calibration of Output Impedance | Yes | Yes |
IEEE 1500 Test Support | Yes | Yes |
Autonomous Test Support | Yes | Yes |
SSO Noise Reduction | Yes | Yes |
Micro-bump Pitch Matched to the DRAM Pitch | Yes | Yes |
Metal Stack | 15 layers | 13 or 15 layers |
Orientation | East-West | East-West |
Register Interface for State Observation | Yes | Yes |
LabStation™ Software Environment for System Level Bring-up, Characterization, and Validation | Yes | Yes |
HBM is a high-performance memory standard that features reduced power consumption and a small form factor. It combines 2.5D packaging with a wider interface at a lower clock speed (as compared to GDDR6) to deliver higher overall throughput at a higher bandwidth-per-watt efficiency for AI/ML and high-performance computing (HPC) applications.
HBM3 Memory Subsystem Example
2.5D/3D System Architecture with HBM3 Memory
Rambus HBM memory subsystems consist of co-validated controller and PHY cores. These cores can also be licensed separately to be paired with 3rd-party or customer controller or PHY solutions.
Rambus HBM memory subsystems support data rates up to 8.4 Gb/s per data pin (HBM3). With its 1024-bit interface and this maximum data rate, it can deliver a memory bandwidth of 1075.2 GB/s.
The interface is designed for a 2.5D system with an interposer used for routing signals between the 3D DRAM stack and the memory subsystem on the SoC. This combination of signal density and stacked form factor requires special design consideration. In order to enable easy implementation and improved flexibility of design, Rambus performs complete signal and power integrity analysis on the entire 2.5D system to ensure that all signal, power and thermal requirements are met.
The Rambus HBM3 memory PHY is available on an advanced process node. Please contact Rambus for details.