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HBM Memory Controller and PHY IP

Delivering ultra high-bandwidth, low-latency memory performance
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HBM Memory Interface Subsystem IP

Rambus High-Bandwidth Memory (HBM) 3.0 and 2E/2 controller, PHY and memory interface subsystems provide high-bandwidth, low-latency memory performance for AI/ML, graphics and HPC applications. 

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HBM Controller
HBM PHY
HBM Memory Subsystem
VersionMaximum Data Rate (Gb/s)SubsystemControllerPHY
HBM38.4Download HBM3 Product Brief Product BriefDownload HBM3 Product Brief Product BriefDownload HBM3 Product Brief Product Brief
HBM2E/23.6/2.0Download HBM3 Product Brief Product BriefDownload HBM3 Product Brief Product BriefDownload HBM3 Product Brief Product Brief

HBM3 & HBM2E Controller IPs

FeaturesHBM3
Product Brief		HBM2E/2
Product Brief
Speed Bins (Gb/s) Up to 8.4Up to 3.6/2.0
Channel Densities (Gb)Up to 32Up to 24
Channels/Pseudo-Channels16/328/16
DRAM StacksUp to 16Up to 12
PHY InterfaceDFI StyleDFI Style
PHY Independent ModeYesYes
Refresh Management SupportYes 
Look-Ahead Command Processing
for Minimum Latency		YesYes
Integrated Reorder FunctionalityYesAdd-on core
Self-refresh and Power-down
Low Power Modes		YesYes
RAS FeaturesYesYes
Built-in Activity MonitorYesYes
DFI CompatibleYesYes
End-to-end Data ParityYesYes
Interface to LogicNative or AXINative or AXI

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HBM3 & HBM2E PHY IP

Features HBM3 Product Brief HBM2E/2 Product Brief
Speed Bins (Gb/s) Up to 8.4 Up to 3.6
Channel Densities (Gb) Up to 32 Up to 24
Channels/Pseudo-Channels 16/32 8/16
DRAM Stacks Up to 16 Up to 12
Controller Interface DFI Style DFI Style
PHY Independent Mode Yes Yes
Selectable Low-Power Operating States Yes Yes
Programmable Output Impedance Yes Yes
Pin Programmable Support for Lane Repair Yes Yes
ZQ Calibration of Output Impedance Yes Yes
IEEE 1500 Test Support Yes Yes
Autonomous Test Support Yes Yes
SSO Noise Reduction Yes Yes
Micro-bump Pitch Matched to the DRAM Pitch Yes Yes
Metal Stack 15 layers 13 or 15 layers
Orientation East-West East-West
Register Interface for State Observation Yes Yes
LabStation™ Software Environment for System Level Bring-up, Characterization, and Validation Yes Yes

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Complete HBM3 Memory Subsystem Solution

HBM is a high-performance memory standard that features reduced power consumption and a small form factor. It combines 2.5D packaging with a wider interface at a lower clock speed (as compared to GDDR6) to deliver higher overall throughput at a higher bandwidth-per-watt efficiency for AI/ML and high-performance computing (HPC) applications. 

HBM3 Memory Subsystem Example

HBM3 Memory Subsystem Example

2.5D/3D System Architecture with HBM3 Memory

2.5D/3D System Architecture with HBM3 Memory

Rambus HBM memory subsystems consist of co-validated controller and PHY cores. These cores can also be licensed separately to be paired with 3rd-party or customer controller or PHY solutions.

Rambus HBM memory subsystems support data rates up to 8.4 Gb/s per data pin (HBM3). With its 1024-bit interface and this maximum data rate, it can deliver a memory bandwidth of 1075.2 GB/s.

The interface is designed for a 2.5D system with an interposer used for routing signals between the 3D DRAM stack and the memory subsystem on the SoC. This combination of signal density and stacked form factor requires special design consideration. In order to enable easy implementation and improved flexibility of design, Rambus performs complete signal and power integrity analysis on the entire 2.5D system to ensure that all signal, power and thermal requirements are met. 

HBM3 Memory: Break Through to Greater Bandwidth

HBM3 Memory: Break Through to Greater Bandwidth
AI/ML’s demands for greater bandwidth are insatiable, driving rapid improvements in every aspect of computing hardware and software. HBM memory is the ideal solution for the high bandwidth requirements of AI/ML training, but it entails additional design considerations given its 2.5D architecture. Now we’re on the verge of a new generation of HBM that will raise memory and capacity to new heights. Designers can realize new levels of performance with the HBM3-ready memory subsystem solution from Rambus. 
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Frequently Asked Questions about HBM

HBM is a high-performance memory standard that delivers extremely high bandwidth at excellent power efficiency by employing a wide 1024-bit interface at relatively low data rates.
HBM3 memory raises the data rate to 6.4 Gb/s to deliver 819.2 GB/s of bandwidth per HBM3 memory device. The Rambus HBM3 memory interface subsystem, comprised of PHY and digital controller, can operate at 8.4 Gb/s to provide additional design margin.
HBM memory offers excellent bandwidth and capacity with superior power efficiency that makes it an ideal solution for AI/ML training workloads.
To achieve its high bandwidth, HBM uses a 1024-bit wide data interface. This is far more than can be supported on a standard PCB used by traditional (2D) memory solutions. So, HBM employs a silicon interposer where traces can be very finely etched. This architecture is called 2.5D. In addition, HBM uses 3D-stacked memory devices, giving HBM a 2.5D/3D architecture.
HBM3 memory is ideal for data-intensive applications like AI/ML, graphics, and HPC, where large amounts of data need to be processed at very high bandwidth.

The Rambus HBM3 memory PHY is available on an advanced process node. Please contact Rambus for details.

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