Delivering ultra high-bandwidth, low-latency memory performance
Rambus High-Bandwidth Memory (HBM) 3.0 and 2E/2 controller IP provide high-bandwidth, low-latency memory performance for AI/ML, graphics and HPC applications.
|Speed Bins (Gb/s)||Up to 9.6||Up to 3.6/2.0|
|Channel Densities (Gb)||Up to 32||Up to 24|
|DRAM Stacks||Up to 16||Up to 12|
|PHY Interface||DFI Style||DFI Style|
|PHY Independent Mode||Yes||Yes|
|Refresh Management Support||Yes|
|Look-Ahead Command Processing|
for Minimum Latency
|Integrated Reorder Functionality||Yes||Add-on core|
|Self-refresh and Power-down|
Low Power Modes
|Built-in Activity Monitor||Yes||Yes|
|End-to-end Data Parity||Yes||Yes|
|Interface to Logic||Native or AXI||Native or AXI|
HBM is a high-performance memory standard that features reduced power consumption and a small form factor. It combines a 2.5D/3D architecture with a wider interface at a lower clock speed (as compared to GDDR6) to deliver higher overall throughput at a higher bandwidth-per-watt efficiency for AI/ML and high-performance computing (HPC) applications.
Rambus HBM memory controllers support data rates up to 9.6 Gb/s per data pin (HBM3). With its 1024-bit interface and this maximum data rate, it can deliver memory throughput of 1.23 TB/s.
Rambus HBM controllers can be paired with 3rd-party or customer PHY solutions.
HBM3 memory raises the data rate to 6.4 Gb/s to deliver 819.2 GB/s of bandwidth per HBM3 memory device. The Rambus HBM3 digital controller can operate at 9.6 Gb/s to provide additional design margin.
To achieve its high bandwidth, HBM uses a 1024-bit wide data interface. This is far more than can be supported on a standard PCB used by traditional (2D) memory solutions. So, HBM employs a silicon interposer where traces can be very finely etched. This structure is called 2.5D. In addition, HBM uses 3D-stacked memory devices, giving HBM a 2.5D/3D architecture.