HBM2E is a high-performance memory that features reduced power consumption and a small form factor. It combines a 2.5D/3D architecture with a 1024-bit wide interface operating at a lower clock speed (as compared to GDDR6) to deliver higher overall throughput at a higher bandwidth-per-watt efficiency for AI/ML and HPC applications.
The Rambus HBM2E controller supports both HBM2 and HBM2E devices with data rates of up to 3.6 Gbps per data pin. It supports all standard channel densities including 4, 6, 8, 12, 16 and 24 Gb. The controller maximizes memory bandwidth and minimizes latency via Look-Ahead command processing. The core is DFI compatible (with extensions added for HBM2E) and supports AXI or native interface to user logic.
The Rambus HBM2E controller is fully compliant with the JEDEC HBM2E JESD235 standard. It supports data rates up to 3.6 Gbps per data pin. The interface features 8 independent channels, each containing 128 bits for a total data width of 1024 bits. The resulting bandwidth is 461 GB/s per HBM2E memory device containing 2, 4, 8 or 12 3D-stacked DRAM.
The Rambus HBM2E controller together with the customer’s choice of PHY comprise a complete HBM2E memory interface subsystem.
Delivering unrivaled memory bandwidth in a compact, high-capacity footprint, has made HBM the memory of choice for AI/ML and other high-performance computing workloads. HBM3 as the latest generation of the standard raises data rates to 6.4 Gb/s and promises to scale even higher. The Rambus HBM3 controller provides industry-leading support of the extended roadmap for HBM3 with performance to 9.6 Gb/s.
|Protocol||Data Rate (Gbps) Max.||Application|
|HBM2E||3.6||AI/ML, HPC and Graphics|
|HBM2||2||AI/ML, HPC and Graphics|