Optimizing Capacity, Connectivity and Capability of the Cloud
At Rambus, we create cutting-edge semiconductor and IP products, spanning memory and interfaces to security, smart sensors and lighting.
High-speed interconnects between chips, and between processors and memory, move enormous volumes of data and are key to meeting target performance of advanced computing architectures.
Rambus provides state-of-the-art interconnect and memory interface IP including complete subsystem solutions, consisting of digital controller and PHY IP, for PCIe®, CXL™, HBM, GDDR and DDR standards. Rambus also offers digital controller IP for the LPDDR and MIPI® standards, as well as a suite of Video Compression and Forward Error Correction IP. Rambus high-speed SerDes PHYs address advanced networking, 5G, chip-to-chip and die-to-die applications.
Interconnect Subsystem IP
Rambus silicon-proven, high-performance PCIe interconnect subsystem, digital controller and PHY IP cores are optimized for use in SoCs, ASICs and FPGAs. These market-leading solutions for high-performance interfaces address AI/ML, data center and edge applications.
Rambus CXL interconnect subsystem, digital controller and PHY IP provide industry-leading performance in SoCs, ASICs and FPGAs. These high-performance interconnect solutions address AI/ML, data center and edge applications.
Optimized for power and area, Rambus multi-protocol SerDes PHYs deliver maximum performance and flexibility for today’s most challenging systems, including D2D, data center, high-speed networking and 5G infrastructure applications.
Silicon-proven, high-performance MIPI CSI-2 and DSI-2 controller cores are optimized for use in SoCs, ASICs and FPGAs. An available MIPI testbench provides the capability for end-to-end simulations of MIPI designs.
Memory Interface Subsystem IP
Rambus offers HBM3 memory interface subsystem IP with performance to 8.4 Gb/s. Rambus HBM memory interface subsystems, digital controllers and PHYs address AI/ML, graphics and HPC applications.
Rambus offers GDDR6 memory interface subsystem with an industry-leading data rate performance of 24 Gb/s. The Rambus GDDR memory interface subsystem, controller and PHY provide high-bandwidth, low-latency memory for AI/ML, graphics and networking applications.
Rambus LPDDR digital controllers deliver high memory bandwidth and throughput for low power applications including mobile, automotive, Internet of Things (IoT) and edge networking devices.
Rambus offers DDR4 and DDR3 memory interface IP delivering industry-leading data rates of up to 3200 MT/s. The DDR memory subsystems, digital controllers and PHYs are available on trusted foundry process nodes for government applications.
Video Compression & Forward Error Correction IP
Rambus silicon-proven VESA DSC and VESA VDC-M IP cores provide visually lossless video compression and enable designers to create cutting-edge displays for mobile, AR/VR and automotive applications. These solutions support both ASIC and FPGA designs.
Rambus Forward Error Correction (FEC) IP cores ensure a glitch-free visual experience for end users when VESA DSC video compression is used in DisplayPort 1.4 and HDMI 2.1 applications. These solutions support both ASIC and FPGA designs.
Data Center Evolution: The Leap to 64 GT/s Signaling with PCI Express 6.0
The PCI Express® (PCIe®) interface is the critical backbone that moves data at high bandwidth and low latency between various compute nodes such as CPUs, GPUs, FPGAs, and workload-specific accelerators. With the torrid rise in bandwidth demands of advanced workloads such as AI/ML training, PCIe 6.0 jumps signaling to 64 GT/s with some of the biggest changes yet in the standard.
Markets
Data Center
AI & ML
Edge
Automotive
Government
IoT
