Compute Express Link (CXL) Controller IP

Delivering high-bandwidth cache-coherent interconnect performance

CXL Controller IP

Rambus high-performance Compute Express Link®™ (CXL®™) 3.0 and 2.0 controllers are optimized for use in SoCs, ASICs and FPGAs. These industry-leading solutions for high-performance interfaces address AI/ML, data center and edge applications.

Version Maximum Data Rate (GT/s) Controller Controller with AXI
CXL 3.1 64 Download the CXL 2.0/1.1 Controller Product Brief Product Brief Download the CXL 2.0/1.1 Controller Product Brief Product Brief
CXL 2.0/1.1 32 Download the CXL 2.0/1.1 Controller Product Brief Product Brief Download the CXL 2.0/1.1 Controller Product Brief Product Brief

CXL Controller IP

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Feature CXL 3.1 Controller CXL 2.0 Controller
Data Rate (GT/s) 64 32
Protocols Supported CXL.io CXL.mem CXL.cache CXL.io CXL.mem CXL.cache
Lane Configurations x1, x2, x4, x8, x16 x1, x2, x4, x8, x16
PIPE Specification Support PIPE 6.x with 8, 16, 32, 64 and 128-bit configurable PIPE interface width PIPE 5.x with 8, 16, 32, 64 and 128-bit configurable PIPE interface width
Silicon Implementation Host, Device, Switch Ports, Dual Mode/Shared Host, Device, Dual Mode/Shared
QuickBoot Mode Optional Optional
Backward Compatibility 2.0, 1.1 1.1
Integrity and Data Encryption (IDE) Included Included

CCIX Controller IP

Version Maximum Data Rate (GT/s) Controller Controller with AXI
1.1 32 Download CCIX 1.1 Controller Product Brief Product Brief Download CCIX 1.1 Controller Product Brief Product Brief

CXL Interconnect Subsystem

The Rambus CXL Controller leverages a silicon-proven PCIe controller architecture for the CXL.io path, and adds CXL.cache and CXL.mem paths specific to the CXL standard. The controller exposes a native Tx/Rx user interface for CXL.io traffic as well as an Intel CXL-cache/mem Protocol Interface (CPI) for CXL.mem and CXL.cache traffic.

The provided Graphical User Interface (GUI) Wizard allows designers to tailor the IP to their exact requirements, by enabling, disabling, and adjusting a vast array of parameters, including CXL device type, PIPE interface configuration, buffer sizes and latency, low power support, SR-IOV parameters, etc. for optimal throughput, latency, size and power.

CXL 2.0 Controller Block Diagram
CXL 3.1 Controller Block Diagram

The controller can be delivered standalone or integrated with the customer’s choice of CXL 3/PCIe 6 PIPE compliant SerDes. It can also be provided with example reference designs for integration with FPGA SerDes.

CXL Memory Initiative: Enabling a New Era of Data Center Architecture

Download our white paper: CXL Memory Initiative: Enabling a New Era of Data Center Architecture

In response to an exponential growth in data, the industry is on the threshold of a groundbreaking architectural shift that will fundamentally change the performance, efficiency and cost of data centers around the globe. Server architecture, which has remained largely unchanged for decades, is taking a revolutionary step forward to address the growing demand for data and the voracious performance requirements of advanced workloads.

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