Delivering high-bandwidth cache-coherent interconnect performance
Home > Interface IP > CXL Interconnect Subsystem IP
Rambus high-performance Compute Express Link™ (CXL™) 3.0 and 2.0 controllers, PHYs and subsystems are optimized for use in SoCs, ASICs and FPGAs. These industry-leading solutions for high-performance interfaces address AI/ML, data center and edge applications.
Version | Maximum Data Rate (GT/s) | Controller | Controller with AXI | PHY |
---|---|---|---|---|
CXL 3.0 | 64 | |||
CXL 2.0/1.1 | 32 |
Feature | CXL 2.0 Controller |
---|---|
Data Rate (GT/s) | 32 |
Protocols Supported | CXL.io CXL.mem CXL.cache |
Lane Configurations | x1, x2, x4, x8, x16 |
PIPE Specification Support | PIPE 5.x with 8, 16, 32, 64 and 128-bit configurable PIPE interface width |
Silicon Implementation | Host, Device, Dual Mode/Shared |
Physical Functions (PF) | Up to 64 |
Virtual Functions (VF) | 512 |
PCIe Express Advanced Error Reporting (AER) | Yes |
QuickBoot Mode | Optional |
Backward Compatibility | 1.1 |
Feature | CXL 3.0 PHY | CXL 2.0/1.1 PHY |
---|---|---|
Data Rate (GT/s) | Up to 64 | Up to 32 |
Controller Interface | PIPE 6.0 | PIPE 5.1 |
Backward Compatibility | 2.0, 1.1 | |
Multi-tap Tx Finite Impulse Response (FIR) Equalizer with Multi-level De-emphasis | Yes | Yes |
Compensation for >36dB Channel Insertion Loss Across PVT | Yes | Yes |
Floating DFE Tap Compensation for Reflection up to 40UI | Yes | |
Tx/Rx Spread Spectrum Clocking for EMI | Yes | Yes |
Built-in Self-Test with ATPG and AC/DC Boundary Scan | Yes | Yes |
Built-in PRBS | Yes | Yes |
In-situ Real-time Monitoring and Receive Data Eye Schmoo | Yes | Yes |
Automatic Calibration of Key Circuits | Yes | Yes |
LabStation™ Software Environment for System Level Bring-up, Characterization, and Validation | Yes | Yes |
Version | Maximum Data Rate (GT/s) | Controller | Controller with AXI |
---|---|---|---|
1.1 | 32 |
The Rambus CXL 2.0 Controller leverages a silicon-proven PCIe 5.0 controller architecture for the CXL.io path, and adds CXL.cache and CXL.mem paths specific to the CXL standard. The controller exposes a native Tx/Rx user interface for CXL.io traffic as well as an Intel CXL-cache/mem Protocol Interface (CPI) for CXL.mem and CXL.cache traffic.
The provided Graphical User Interface (GUI) Wizard allows designers to tailor the IP to their exact requirements, by enabling, disabling, and adjusting a vast array of parameters, including CXL device type, PIPE interface configuration, buffer sizes and latency, low power support, SR-IOV parameters, etc. for optimal throughput, latency, size and power.
The Rambus CXL 2.0 (PCIe 5.0) PHY is a low-power, area-optimized, silicon IP core designed with a system-oriented approach to maximize flexibility and ease of integration. It delivers up to 32 GT/s signaling rates in performance-intensive applications for artificial intelligence (AI), data center, edge, 5G infrastructure and graphics.
Together, the Rambus CXL 2.0 Controller and PHY provide a complete CXL interconnect subsystem.
In response to an exponential growth in data, the industry is on the threshold of a groundbreaking architectural shift that will fundamentally change the performance, efficiency and cost of data centers around the globe. Server architecture, which has remained largely unchanged for decades, is taking a revolutionary step forward to address the growing demand for data and the voracious performance requirements of advanced workloads.