At Rambus, we create cutting-edge semiconductor and IP products, spanning memory and interfaces to security, smart sensors and lighting.
Compute Express Link IP
Delivering high-bandwidth cache-coherent interconnect performance
CXL Controller IP
Rambus high-performance Compute Express Link™ (CXL™) 2.0 controllers are optimized for use in SoCs, ASICs and FPGAs. These industry-leading solutions for high-performance interfaces address AI/ML, data center and edge applications.
| Version | Maximum Data Rate (GT/s) | Controller | Controller with AXI |
|---|---|---|---|
| CXL 2.0/1.1 | 32 |  Product Brief |
Product Brief |
CXL Controller IP
| Feature | CXL 2.0 Controller |
|---|---|
| Data Rate (GT/s) | 32 |
| Protocols Supported | CXL.io CXL.mem CXL.cache |
| Lane Configurations | x1, x2, x4, x8, x16 |
| PIPE Specification Support | PIPE 5.x with 8, 16, 32, 64 and 128-bit configurable PIPE interface width |
| Silicon Implementation | Host, Device, Dual Mode/Shared |
| Physical Functions (PF) | Up to 64 |
| Virtual Functions (VF) | 512 |
| PCIe Express Advanced Error Reporting (AER) | Yes |
| QuickBoot Mode | Optional |
| Backward Compatibility | 1.1 |
CCIX Controller IP
| Version | Maximum Data Rate (GT/s) | Controller | Controller with AXI |
|---|---|---|---|
| 1.1 | 32 | Product Brief |
Product Brief |
CXL Interconnect Subsystem
The Rambus CXL 2.0 Controller leverages a silicon-proven PCIe 5.0 controller architecture for the CXL.io path, and adds CXL.cache and CXL.mem paths specific to the CXL standard. The controller exposes a native Tx/Rx user interface for CXL.io traffic as well as an Intel CXL-cache/mem Protocol Interface (CPI) for CXL.mem and CXL.cache traffic.
The provided Graphical User Interface (GUI) Wizard allows designers to tailor the IP to their exact requirements, by enabling, disabling, and adjusting a vast array of parameters, including CXL device type, PIPE interface configuration, buffer sizes and latency, low power support, SR-IOV parameters, etc. for optimal throughput, latency, size and power.
Rambus provides integration and validation of the CXL 2.0 digital controller with the customer’s choice of 3rd-party CXL 2.0 (PCIe® 5.0) PHY.
CXL Memory Interconnect Initiative: Enabling a New Era of Data Center Architecture
In response to an exponential growth in data, the industry is on the threshold of a groundbreaking architectural shift that will fundamentally change the performance, efficiency and cost of data centers around the globe. Server architecture, which has remained largely unchanged for decades, is taking a revolutionary step forward to address the growing demand for data and the voracious performance requirements of advanced workloads.
Controller
- Verilog RTL (source code)
- Libraries for functional simulation
- Configuration assistant GUI (Wizard)
- PCIe bus functional model
- Reference designs
- Complete documentation
Controller
- Expert technical support
- Maintenance updates
- Customization
- SoC Integration
