CXL 2.0 Controller

Rambus Compute Express Link (CXL) 2.0 Controller (formerly XpressLINK) leverages a silicon-proven PCIe 5.0 controller architecture for the CXL.io path, and adds CXL.cache and CXL.mem paths specific to the CXL standard. The controller exposes a native Tx/Rx user interface for CXL.io traffic as well as an Intel CXL-cache/mem Protocol Interface (CPI) for CXL.mem and CXL.cache traffic. There is also an CXL 2.0 Controller with AXI version (formerly XpressLINK-SOC) for ASIC and FPGA implementations with support for the AMBA AXI protocol specification for CXL.io and either CPI or AXI for CXL.mem, and CPI for CXL.cache or the AMBA CXS-B protocol specification. With the Rambus CXL 2.0 SerDes PHY, it comprises a complete CXL interconnect subsystem.

How the CXL 2.0 Controller Works

The controller supports the CXL 2.0 specification and is backward compatible with CXL 1.1. It complies with the Intel PHY Interface for PCI Express (PIPE) specification version 5.x. The provided Graphical User Interface (GUI) Wizard allows designers to tailor the IP to their exact requirements, by enabling, disabling, and adjusting a vast array of parameters, including CXL device type, PIPE interface configuration, buffer sizes and latency, low power support, SR-IOV parameters, etc. for optimal throughput, latency, size and power. The controller has been extensively verified using commercial and internally developed VIP and test suites, and integrates with the Rambus CXL/PCIe 5.0 PHY for a complete CXL interface subsystem. Alternatively, it can be paired with a number of 3rd-party CXL PHYs.

Watch a demonstrate the Rambus Controller IP for CXL 2.0 and the CXL.mem protocol used to access Host-managed Device Memory
Play Video about Watch a demonstrate the Rambus Controller IP for CXL 2.0 and the CXL.mem protocol used to access Host-managed Device Memory

Watch a video demo of our Controller IP for CXL 2.0 and the CXL.mem protocol used to access Host-managed Device Memory.

CXL 2.0 Controller Block Diagram
CXL 2.0 Controller Block Diagram
CXL 2.0 Controller with AXI Block Diagram
CXL 2.0 Controller with AXI Block Diagram

The CXL 2.0 controller has been extensively verified using commercial and internally developed VIP and test suites.

CXL Memory Interconnect Initiative: Enabling a New Era of Data Center Architecture

CXL Memory Interconnect Initiative: Enabling a New Era of Data Center Architecture

In response to an exponential growth in data, the industry is on the threshold of a groundbreaking architectural shift that will fundamentally change the performance, efficiency and cost of data centers around the globe. Server architecture, which has remained largely unchanged for decades, is taking a revolutionary step forward to address the growing demand for data and the voracious performance requirements of advanced workloads. 

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