Protecting data in use
Rambus inline memory encryption and inline cipher engines protect data in use including applications for secure memory transactions between hosts and attached memory at high throughput with low latency. Differential Power Analysis (DPA) protection and Data Path Integrity is available as an option on most solutions as a counter to DPA and related side-channel attacks.
|Inline memory encryption engine for ASIC SoCs. AES-XTS/GCM and SM4-XTS/GCM encryption, decryption, integrity and authentication. DPA protection option. Channelized with 128-bit AXI4 master/slave interface. Includes native key management.
|Inline memory encryption engine, for FPGA. AES-GCM mode. DPA protection option. Channelized with 128-bit AXI master/slave interface. Includes memory manager, last level cache and native key management.
|Inline cipher engine with AXI, for memory encryption. AES-XTS/GCM, SM4-XTS/GCM. DPA protection option. Channelized with 128-bit AXI master/slave interface.
|Inline cipher engine, for memory encryption. AES-XTS/GCM, SM4-XTS/GCM. DPA protection option. Channelized with inline native interface.
|Inline cipher engine for PCIe, CXL, NVMe, 5G FlexE link integrity and data encryption (IDE) using AES GCM mode. Channelized with inline native interface.
The MACsec, IPsec and SSL/TLS/DTLS protocols are the primary means of securing data in motion (communicated between connected devices). These protocols can be anchored in hardware or implemented in software as part of an end-to-end security architecture. This white paper provides fundamental information on each of these protocols including their interrelationships and use cases.