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CCIX 1.1 Controller
The CCIX 1.1 Controller (formerly XpressCCIX) is a configurable and scalable PCIe controller IP designed for ASIC and FPGA implementations. There is also a CCIX 1.1 Controller with AXI version (formerly XpressCCIX-AXI) with support for the AMBA AXI protocol specification.
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CCIX 1.1How the CCIX 1.1 Controller Works
The CCIX 1.1 Controller IP supports the PCI Express 5.0, 4.0 and 3.1/3.0 specifications, as well as with version 4.x and 5.x of the PHY Interface for PCI Express (PIPE) specification, and supports the CCIX Extended Speed Mode as defined in the CCIX Base Specification Revision 1.1. The IP can be configured to support endpoint, root port, switch port, and dual-mode topologies, allowing for a variety of use models.
The provided Graphical User Interface (GUI) Wizard allows designers to tailor the IP to their exact requirements, by enabling, disabling, and adjusting a vast array of parameters, including CCIX ESM mode, data path size, PIPE interface width, low power support, SR-IOV, ECC, AER, etc. for optimal throughput, latency, size and power.
The CXL 2.0 controller has been extensively verified using commercial and internally developed VIP and test suites. It integrates with the Rambus CXL/PCIe 5.0 PHY for a complete CXL 2.0 interface subsystem. Alternatively, it can be paired with a number of 3rd-party CXL 2.0 PHYs.
Data Center Evolution: Accelerating Computing with PCI Express 5.0
The PCI Express® (PCIe) interface is the critical backbone that moves data at high bandwidth between various compute nodes such as CPUs, GPUs, FPGAs, and workload-specific accelerators. The rise of cloud-based computing and hyperscale data centers, along with high-bandwidth applications like artificial intelligence (AI) and machine learning (ML), require the new level of performance of PCI Express 5.0.
Solution Offerings
CCIX 1.1 Controller
PCI Express layer
- Supports the PCI Express 5.0, 4.0, 3.1/3.0, and PIPE 4.x (8-, 16-, 32- and 64-bit) specifications
- Compliant with PCI-SIG Single-Root I/O Virtualization (SR-IOV) Specification
- Supports Endpoint, Root-Port, Dual-mode, Switch port configurations
- Supports x16, x8, x4, x2, x1 at 32 GT/s, 16 GT/s, 8 GT/s, 5 GT/s, 2.5 GT/s speeds
- Supports AER, ECRC, ECC, MSI, MSI-X, Multi-function, P2P, crosslink, and other optional features
- Additional optional features include OBFF, TPH, ARI, LTR, IDO, L1 PM substates, etc.
CCIX Support
- Implements DVSEC Capability as per CCIX Base Specification Rev. 1.0
- Supports CCIX ESM DataRate0 at 20 Gb/s and DataRate1 at 25 Gb/s
User Interface layer
- 512-bit transmit/receive low-latency user interface
- User-selectable Transaction/Application Layer clock frequency
- Sideband signaling for PCIe configuration access, internal status monitoring, debug, and more
- Optional Transaction Layer bypass
Integrity and Data Encryption (IDE)
- Implements the PCI Express IDE ECN
- Configurable IDE engine
- Supports x1 to x16 lanes
- 256-bit or 512-bit data bus for PCIe IDE
- Supports containment and skid modes
- Supports early MAC termination
- Supports multi-stream
- Utilizes high-performance AES-GCM for encryption, decryption, authentication
- PCIe IDE TLP aggregation for 1, 2, 4, 8 TLPs
- PCIe IDE automatic IDE prefix insertion and detection
- PCIe IDE automatic IDE sync/fail message generation
- PCRC calculation & validation
- Efficient key control/refresh
- Bypass mode
Unique Features & Capabilities
- Internal data path size automatically scales up or down (64-, 256-, 512- bits) based on link speed and width for reduced gate count and optimal throughput
- Dynamically adjustable application layer frequency down to 8Mhz for increased power savings
- Optional MSI/MSI-X register remapping to memory for reduced gate count when multi-function or SR-IOV is implemented
- Configurable pipelining enables full speed operation on Intel and Xilinx FPGA, full support for production FPGA designs up to Gen4 x8, Gen3 x16, CCIX 25G x8 with same RTL code (when supported)
- Ultra-low Transmit and Receive latency (excl. PHY)
- Smart buffer management on receive side (Rx Stream) and transmit side (merged Replay/Transmit buffer) enables lower memory footprint
- Advanced Reliability, Availability, Serviceability (RAS) features include LTSSM timers override, ACK/NAK/Replay/UpdateFC timers override, unscrambled PIPE interface access, error injection on Rx and Tx paths, recovery detailed status and much more, allowing for safe and reliable deployment of IP in mission-critical SoCs
- Optional Transaction Layer bypass allows for customer-developed application layer
- Optional QuickBoot mode allows for up to 4x faster link training, cutting system-level simulation time by 20%
CCIX 1.1 Controller with AXI
PCI Express layer
- Supports the PCI Express 5.0, 4.0 or 3.1/3.0, and PIPE (8-, 16-, 32- and 64-bit) specifications
- Compliant with PCI-SIG Single-Root I/O Virtualization (SR-IOV) Specification
- Supports Endpoint, Root-Port, Dual-mode configurations
- Supports x16, x8, x4, x2, x1 at 32 GT/s, 16 GT/s, 8 GT/s, 5 GT/s, 2.5 GT/s speeds
- Supports AER, ECRC, ECC, MSI, MSI-X, Multi-function, P2P, crosslink, and other optional features
- Supports many ECNs including LTR, L1 PM substates, etc.
CCIX Support
- Implements DVSEC Capability as per CCIX Base Specification Rev. 1.1
- Supports CCIX ESM DataRate0 at 20 Gb/s and DataRate1 at 25 Gb/s
AMBA AXI layer
- Compliant with the AMBA® AXI™ Protocol Specification (AXI3, AXI4 and AXI4-Lite) and AMBA® 4 AXI4-Stream Protocol Specification
- Supports multiple, user-selectable AXI interfaces including AXI Master, AXI Slave, AXI Stream
- Each AXI interface data width independently configurable in 256-, 128-, and 64-bit
- Each AXI interface can operate in a separate clock domain
Integrity and Data Encryption (IDE)
- Implements the PCI Express IDE ECN
- Configurable IDE engine
- Supports x1 to x16 lanes
- 256-bit or 512-bit data bus for PCIe IDE
- Supports containment and skid modes
- Supports early MAC termination
- Supports multi-stream
- Utilizes high-performance AES-GCM for encryption, decryption, authentication
- PCIe IDE TLP aggregation for 1, 2, 4, 8 TLPs
- PCIe IDE automatic IDE prefix insertion and detection
- PCIe IDE automatic IDE sync/fail message generation
- PCRC calculation & validation
- Efficient key control/refresh
- Bypass mode
Data engines
- Optional built-in Legacy DMA engine
- Up to 8 DMA channels, Scatter-Gather, descriptor prefetch
- Completion reordering, interrupt and descriptor reporting
- Optional Address Translation tables for direct PCIe to AXI and AXI to PCIe communication
Unique Features & Capabilities
- Internal data path size automatically scales up or down (64-, 256-, 512- bits) based on link speed and width for reduced gate count and optimal throughput
- Dynamically adjustable application layer frequency down to 8Mhz for increased power savings
- Optional MSI/MSI-X register remapping to memory for reduced gate count when multi-function or SR-IOV is implemented
- Configurable pipelining enables full speed operation on Intel and Xilinx FPGA, full support for production FPGA designs up to Gen4 x8, Gen3 x16, CCIX 25G x8 with same RTL code (when supported)
- Ultra-low Transmit and Receive latency (excl. PHY)
- Smart buffer management on receive side (Rx Stream) and transmit side (merged Replay/Transmit buffer) enables lower memory footprint
- Advanced Reliability, Availability, Serviceability (RAS) features include LTSSM timers override, ACK/NAK/Replay/UpdateFC timers override, unscrambled PIPE interface access, error injection on Rx and Tx paths, recovery detailed status and much more, allowing for safe and reliable deployment of IP in mission-critical SoCs
- Optional Transaction Layer bypass allows for customer-developed application layer
- Optional QuickBoot mode allows for up to 4x faster link training, cutting system-level simulation time by 20%
IP files
- Verilog RTL source code
- Libraries for functional simulation
- Configuration assistant GUI
Documentation
PCI Express Bus Functional Model
- Encrypted Simulation libraries
Software
- PCI Express Windows x64 and Linux x64 device drivers
- PCIe C API
Reference Designs
- Synthesizable Verilog RTL source code
- Simulation environment and test scripts
- Synthesis project & DC constraint files (ASIC)
- Synthesis project & constraint files for supported FPGA hardware platforms (FPGA)
Advanced Design Integration Services:
- Integration of commercial and proprietary PCIe PHY IP
- Development and validation of custom PCIe PCS layer
- Customization of the Controller IP to add customer-specific features
- Generation of custom reference designs
- Generation of custom verification environments
- Design/architecture review and consulting
Resources
Videos
Demonstration of a CXL Interconnect on a FPGA-based design
