The Rambus Compute Express Link (CXL) 3.0 Controller is a parameterizable design for ASIC and FPGA implementations. It leverages the Rambus PCIe 6.0 Controller architecture for the CXL.io protocol and adds the CXL.cache and CXL.mem protocols specific to CXL. The controller exposes a native Tx/Rx user interface for CXL.io traffic as well as an Intel CXL-cache/mem Protocol Interface (CPI) for CXL.mem and CXL.
The controller supports the CXL 3.0 specification and is backward compatible with CXL 2.0 and CXL 1.1. It complies with the Intel PHY Interface for PCI Express (PIPE) specification version 6.x. The provided Graphical User Interface (GUI) Wizard allows designers to tailor the IP to their exact requirements, by enabling, disabling, and adjusting a vast array of parameters. This includes CXL device type, PIPE interface configuration, buffer sizes and latency, low power support, SR-IOV parameters, etc. For optimal throughput, latency, size and power. The controller can be optionally delivered integrated with the customer’s choice of CXL 3.0/PCIe6.0 PIPE compliant SerDes.
In response to an exponential growth in data, the industry is on the threshold of a groundbreaking architectural shift that will fundamentally change the performance, efficiency and cost of data centers around the globe. Server architecture, which has remained largely unchanged for decades, is taking a revolutionary step forward to address the growing demand for data and the voracious performance requirements of advanced workloads.
User Interface Layer (Base Version)
AMBA AXI Layer for CXL.io (AXI Version)
Integrity and Data Encryption (IDE)