CXL 3.1 Controller

The Rambus Compute Express Link® (CXL®) 3.1 Controller is a parameterizable design for ASIC and FPGA implementations. It leverages the Rambus PCIe 6.1 Controller architecture for the protocol and adds the CXL.cache and CXL.mem protocols specific to CXL. The controller exposes a native Tx/Rx user interface for traffic as well as an Intel CXL-cache/mem Protocol Interface (CPI) for CXL.mem and CXL.

How the CXL 3.1 Controller Works

The controller supports the CXL 3.1 specification and is backward compatible with CXL 2.0 and CXL 1.1. It complies with the Intel PHY Interface for PCI Express (PIPE) specification version 6.x. The provided Graphical User Interface (GUI) Wizard allows designers to tailor the IP to their exact requirements, by enabling, disabling, and adjusting a vast array of parameters. This includes CXL device type, PIPE interface configuration, buffer sizes and latency, low power support, SR-IOV parameters, etc. For optimal throughput, latency, size and power.

The controller can be delivered standalone or integrated with the customer’s choice of CXL 3/PCIe 6 PIPE compliant SerDes. It can also be provided with example reference designs for integration with FPGA SerDes.

CXL 2.0 Controller Block Diagram
CXL 3.1 Controller Block Diagram

CXL 3.1 Controller Highlights

  • Ultra-low Transmit and Receive latency
  • Internal data path size automatically scales up or down (256, 512 or 1024 bits) based on max. link speed and width for optimal throughput
  • Supports backwards compatibility to PCIe 6.1
  • Optional MSI/MSI-X register remapping to memory for reduced gate count when SR-IOV is implemented
  • Optional QuickBoot mode allows for up to 4x faster link training, cutting system-level simulation time by 20%
  • Loopback Mode support at DLL for CXL.mem and CXL.cache protocols
  • Merged Replay and Transmit buffer enables lower memory footprint
  • RAS feature support beyond CXL specification
  • Architected to support ASIC and FPGA implementation with the same code base

CXL Memory Initiative: Enabling a New Era of Data Center Architecture

Download our white paper: CXL Memory Initiative: Enabling a New Era of Data Center Architecture

In response to an exponential growth in data, the industry is on the threshold of a groundbreaking architectural shift that will fundamentally change the performance, efficiency and cost of data centers around the globe. Server architecture, which has remained largely unchanged for decades, is taking a revolutionary step forward to address the growing demand for data and the voracious performance requirements of advanced workloads.

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