At Rambus, we create cutting-edge semiconductor and IP products, spanning memory and interfaces to security, smart sensors and lighting.
HBM3 Controller
The Rambus HBM3 controller core is designed for use in applications requiring high memory bandwidth and low latency including AI/ML, HPC, advanced data center workloads and graphics.
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Product BriefThe HBM3 Memory Subsystem
HBM3 is a high-performance memory that features reduced power consumption and a small form factor. It combines a 2.5D/3D architecture with a 1024-bit wide interface operating at a lower clock speed (as compared to GDDR6) to deliver higher overall throughput at a higher bandwidth-per-watt efficiency for AI/ML and HPC applications.
The Rambus HBM3 memory controller supports data rates up to 9.6 Gbps per data pin. The interface features 16 independent channels, each containing 64 bits for a total data width of 1024 bits. At maximum data rate, this provides a total interface bandwidth of 1229 GB/s.
The Rambus HBM3 memory controller supports HBM3 memory devices with 2, 4, 8, 12 and 16 DRAM stack height with densities of up 32 Gb. The subsystem maximizes bandwidth and latency via Look-Ahead command processing.
The Rambus HBM3 memory controller combined with the customer’s choice of PHY comprises a complete HBM3 memory subsystem.
HBM3 Memory: Breakthrough to Greater Bandwidth
Delivering unrivaled memory bandwidth in a compact, high-capacity footprint, has made HBM the memory of choice for AI/ML and other high-performance computing workloads. HBM3 as the latest generation of the standard raises data rates to 6.4 Gb/s and promises to scale even higher. The Rambus HBM3 controller provides industry-leading support of the extended roadmap for HBM3 with performance to 9.6 Gb/s.
Solution Offerings
- Supports HBM3 memory devices
- Supports all standard HBM3 channel densities (up to 32 Gb)
- Supports up to 9.6 Gbps/pin
- Refresh Management (RFM) support
- Maximizes memory bandwidth and minimizes latency via Look-Ahead command processing
- Integrated Reorder functionality
- Achieves high clock rates with minimal routing constraints
- Self-refresh and Power-down Low Power Modes
- Support for HBM3 RAS features
- Built-in hardware-level performance Activity Monitor
- DFI compatible
- End-to-end data parity
- Supports AXI or native interface to user logic
- Core (source code)
- Testbench (source code)
- Complete documentation
- Expert technical support
- Maintenance updates
Engineering Design Services:
- Customization
- SoC Integration
Protocol Compatibility
| Protocol | Data Rate (Gbps) Max. | Application |
|---|---|---|
| HBM3 | 4.8, 5.6, 6.4, 8.4, 9.6 | AI/ML, HPC, Graphics |
