FlexPhase technology anticipates the phase difference between signals on different traces and manages the transmission of data bits so that the data arrives at the memory device with a known timing relationship with respect to the command and address signals sent to the memory device. It can also be used to enhance conventional DRAM architectures by managing the variation in signal propagation times due to variations in trace lengths.
In DRAM systems, FlexPhase circuits can be used to optimize data and strobe placement. FlexPhase circuits can also be used to finely tune the timing relationships between data, command, address and clock signals. In conventional DRAM architectures, FlexPhase circuits can be used to deskew incoming signals at the controller in order to compensate for uncertainty in the arrival times of signals. Further, FlexPhase circuits can be used to intentionally inject a timing offset – “preskew” data such that the data will arrive at the DRAM devices coincident with the command/address or clock signal. FlexPhase minimizes the systematic timing errors in typical memory systems by adjusting transmit and receive phase offsets at each pin or pin-group.
When using a Fly-by architecture, the amount of time required for the data, strobe, command, address and clock signals to propagate between the memory controller and DRAMs is primarily affected by the lengths of the traces between the controller and the DRAM devices over which the signals propagate. In a Fly-by system, the command, address and clock signals arrive at each DRAM at different times, which in turn results in the data signals being transmitted from each DRAM device at different times. FlexPhase can be used at the controller to deskew those data signals to eliminate the offset due to the Fly-by architecture in addition to any inherent timing offsets of the system. Similarly, because the command, address and clock signals arrive at each DRAM at different times, the data for write operations to the memory devices needs to be preskewed by the controller to account for the difference in when the memory devices will be expecting the write data. FlexPhase can accomplish that preskewing while still eliminating inherent timing offsets in the system.
FlexPhase is a departure from traditional serial link technologies in which timing deskew is performed using an embedded clock. Such deskewing techniques, which typically rely on 8b/10b encoding to ensure adequate transition density for clock recovery, require more chip area, have added power consumption, increase latency, and suffer a 20 percent bandwidth penalty associated with the 8b/10b encoding.
FlexPhase includes in-system timing characterization and self-test functionality that enables aggressive timing