Mobile devices and their associated applications are “bursty” in nature—spending the majority of the time in stand-by, and performing sporadic requests rather than a con-stant stream of processes. In order to provide superior performance and optimal power efficiency across all operating modes requires a mobile memory architecture that is ca-pable of switching quickly between active and idle (or power down) states and back again.
Clock power is saved by synchronously “pausing” the clock distribution at its root which cleanly turns off clocks to circuitry in both the controller and the DRAM. As shown in the figure below, the root of the distribution circuitry is located at the output of the clock multiplier located in the PLL block.
The design supports three low-power states and one active state which are responsive to command traffic from the memory controller. These states are described in the table below:
|P1 – Deep Power Down||Only leakage power is consumed|
|P2 – Power Down||Only the clock multiplier is turned on|
|P3 – Idle||The clock distribution is paused|
|P4 – Active||The memory controller interface and DRAM interface are active|
The ideal mobile device would spend it’s stand-by time drawing near-zero power while remaining at-the-ready to quickly answer calls, get directions, or check restaurant re-views—fast transition times are key to achieving this level of performance. By improving the total power consumption and responsiveness of a mobile devices, including smartphones and tablets, end-users are able to experience longer batter life, faster wake-up times and a noticeable improvement in system performance.