Modern systems use synchronous communication to achieve high data transmission rates to and from the DRAMs in the memory system. Systems that communicate synchronously use a clock signal as a timing reference so that data can be transmitted and received with a known relationship to this reference. A difficulty in maintaining this relationship is that process, voltage, and temperature variations can alter the timing relationship between the clock and data signals, resulting in reduced timing margins. This problem gets worse as signaling speeds increase, limiting the ability of systems to communicate data at higher speeds.
Timing margins, in particular, can be affected by process, voltage, and temperature at low and high signaling speeds. At low signaling speeds (the left side of Figure 1), DataPVT1 illustrates the relationship of the data valid window (the time over which data can be reliably sampled by the receiver) and the clock for a given set of operating conditions. Likewise, DataPVT2 shows the relationship of the data valid window and the clock for a different set of operating conditions. These two sets of operating conditions represent the operational extremes over which the device functions. Receiver circuitry does not typically understand how the data valid window changes as process, voltage, and temperature change at the transmitter. Because of this, the receiver circuitry is designed to sample data within a window of time that data is valid across all allowed operating conditions. If DataPVT1 and DataPVT2 represent the soonest and latest (relative to the clock signal) data valid windows, then the receiver will assume a data valid window that is the intersection of these two, and choose a sample point within this resulting data valid window that is valid across process, voltage, and temperature variations.
At low signaling speeds, the data valid window (the time over which data can be sampled reliably by the receiver) can be large. Even in the presence of a substantial shift in the data valid window across operational extremes, the resulting data valid window can still be large enough to transmit and receive data reliably. This is the case for DRAM technologies such as SDRAM. However, for higher-speed DRAM technologies such as RDRAM and DDR, variations in process, voltage, and temperature can result in the loss of the data valid window. The right side of Figure 1 shows that at higher signaling speeds, the data valid windows for both DataPVT1 and DataPVT2 are smaller, reflecting the fact that information must be transmitted more quickly at higher signaling rates. Although the data valid windows are smaller, these windows still shift the same amount across process, voltage, and temperature (assuming no manufacturing improvements or changes in operating environment). Because these data valid windows are smaller, the resulting intersection of the data valid windows yields no resulting data valid window during which receiver circuitry can reliably sample data.
As process, voltage, and temperature vary, the timing characteristics of the output logic and output driver change, causing the data valid window to shift. In order to transmit and receive data at high speeds, this timing variation needs to be addressed.