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XpressAGENT™ Add-on Module
Rambus XpressAGENT is a chip-level solution designed for simplifying observability and expediting debug of PCI Express® (PCIe®) and Compute Express Link™ (CXL™) based subsystems that utilize Rambus PCIe or CXL controllers with any PCIe or CXL PHY.
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Product BriefHow the XpressAGENT™ Add-on Module works
The XpressAGENT Add-on Module provides a comprehensive set of capabilities including configuring and initializing the subsystem, logging events, monitoring system performance, and testing for design reliability. It comes equipped with a built-in logic analyzer for advanced visibility of signals through a flexible trigger configuration. The XpressAGENT software API allows for convenient local or remote access to and management of the subsystem’s registers and functionality.
Data Center Evolution: The Leap to 64 GT/s Signaling with PCI Express 6.0
The PCI Express® (PCIe®) interface is the critical backbone that moves data at high bandwidth and low latency between various compute nodes such as CPUs, GPUs, FPGAs, and workload-specific accelerators. With the torrid rise in bandwidth demands of advanced workloads such as AI/ML training, PCIe 6.0 jumps signaling to 64 GT/s with some of the biggest changes yet in the standard.Solution Offerings
Initialization and Configuration
- Saves time and effort by providing required functionality that would otherwise be implemented by the user
- Programmatically configure the Rambus IP configuration pins
- Programmatically configure PHY IP. Can access PHY registers via AMBA AHB or APB
Link Testing/Reliability Testing (user initiated)
- Force Receiver Detect
- Disable low-power negotiation
- Set Loopback Master and generate compliance pattern
- Change initial EQ Presets
- Override LTSSM timeout timers
- Override ACK/NAK, Replay, UpdateFC timers
- Inject errors on Rx and Tx side for all Correctable and Uncorrectable AER errors
- Get detailed information on Recovery state
Real-Time Monitoring/Logging
- Link state (speed, lanes, polarity)
- Equalization status
- Negotiated Max. Payload
- LTSSM state transitions with hardware time- stamping
- Low-power status
- Rx and Tx throughput per packet type
- Reset and Power Management events
- Error events (recovery, framing, encoding, DLLP, TLP, etc.)
Trace Debug Capabilities
- Trace capture in the PCLK (PHY/MAC) domain
- Up to 610 user-selectable signals
- Optional access to PIPE signals (non-Serdes PIPE control/status signals only)
- Includes 32 user-defined inputs
- Trace capture in the TCLK (Transaction Layer) domain
- Up to 576 user-selectable signals
- Includes 32 user-defined inputs
- Separate memory buffers for PCLK and TCLK domain (single-port, single-clock)
- Up to 32K samples for each trace buffer (configurable trace buffer depth)
- Supported trigger conditions: pattern matching and rising or falling edge on selected signals
- Output VCD files allow convenient waveform viewing of signals
- Trace debug functionality can be disabled to save resources
XpressAGENT API
- Abstracts PCIe subsystem memory map
- Simple register acccess functions
- RegisterRead, RegisterWrite
- Available in C/C++, Python, and Verilog+IPXACT
- CPU-agnostic
- Can run on local CPU or remote CPU via UART connection
- Link state (speed, lanes, polarity)
- Equalization status
- Negotiated Max. Payload
- LTSSM state transitions with hardware time- stamping
IP Files
- Verilog RTL source code
- Libraries for functional simulation
- Configuration assistant GUI (Wizard)
- PCI Express Bus Functional Model
Documentation
- IP Reference Manual
- Getting Started Guide
Reference Designs
- Synthesizable Verilog RTL source code
- Simulation environment and test scripts
- Synthesis project and DC constraint files (ASIC)
Resources
Videos
Demonstration of a CXL Interconnect on a FPGA-based design
