PCIe 7.0 Retimer Controller with CXL Support

PCI Express® (PCIe®) 7.0 links operating at 128 GT/s using PAM4 signaling have a reach of up to 13 inches at nominal conditions on standard PCBs. Extending trace routing beyond this distance results in higher first bit error rates (FBER) and reduced link efficiency due to increased link recovery and retransmissions.

As new distributed architectures are deployed in data centers, greater flexibility is desired for chip placement including the need for longer trace lengths. Protocol-aware retimer chips can fully regenerate signals allowing board designers to extend reach and flexibly build various system topologies. The Rambus PCIe 7.0 Retimer Controller provides a complete digital data path solution that delivers best-in-class latency, power and area, and accelerates the time-to-market for PCIe 7.0 retimer chips.

How the PCIe 7.0 Retimer Controller Works

The PCIe 7.0 Retimer provides a highly optimized low-latency data path for signal regeneration. It supports retimer chip PHYs via PIPE 6.2.1 interfaces. The control plane interface is provided via CSR (AHB-lite). The PCIe 7.0 Retimer Controller is CXL protocol aware and supports links using 128 GT/s and lower data rates of PCIe.
PCIe 7.0 Retimer IP Block Diagram
PCIe 7.0 Retimer IP Block Diagram

Data Center Evolution: The Leap to 64 GT/s Signaling with PCI Express 6.1

Download our white paper: Data Center Evolution: The Leap to 64 GT/s Signaling with PCI Express 6.1

The PCI Express® (PCIe®) interface is the critical backbone that moves data at high bandwidth and low latency between various compute nodes such as CPUs, GPUs, FPGAs, and workload-specific accelerators. With the rapid rise in bandwidth demands of advanced workloads such as AI/ML training, PCIe 6.1 jumps signaling to 64 GT/s with some of the biggest changes yet in the standard.

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