PCIe Controller for USB4

The PCIe Controller for USB4 (formerly XpressRICH) is a configurable and scalable PCIe controller IP designed for ASIC and FPGA implementations. There is also a PCIe Controller for USB4 with AXI version (formerly XpressRICH-AXI) with support for the AMBA AXI protocol specification.

How the PCIe Controller for USB4 Works

The PCIe Controller for USB4 IP supports the PCIe 5.0 specification, and implements the required features mandated by the USB4 Specification. The IP can be configured to support endpoint, root port, switch port, and dual-mode topologies, allowing for a variety of use models. The provided Graphical User Interface (GUI) Wizard allows designers to tailor the IP to their exact requirements, by enabling, disabling, and adjusting a vast array of parameters. 

PCIe 5.0 Controller with AXI Block Diagram
PCIe Controller for USB4 Block Diagram
PCIe 5.0 Controller with AXI Block Diagram
PCIe Controller for USB4 with AXI Block Diagram

The PCIe Controller for USB4 enables designers to support tunneling of PCIe in USB4 Devices or Hosts for attaching PCIe devices either internally or externally. By implementing internal PCIe devices in their USB4 designs, designers can differentiate their USB4 ICs while reducing latency and power consumption.

Data Center Evolution: Accelerating Computing with PCI Express 5.0

Data Center Evolution: Accelerating Computing with PCI Express 5.0

The PCI Express® (PCIe) interface is the critical backbone that moves data at high bandwidth between various compute nodes such as CPUs, GPUs, FPGAs, and workload-specific accelerators. The rise of cloud-based computing and hyperscale data centers, along with high-bandwidth applications like artificial intelligence (AI) and machine learning (ML), require the new level of performance of PCI Express 5.0. 

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