Rambus Blog
Hardware Root of Trust: Everything you need to know
Last updated on: October 29, 2021 As explained in our “Secure Silicon IP Webinar Series“,
Rambus Showcases DDR5 RCD at the 2021 Intel ON Digital Event
Are you headed to the digital Intel ON event from October 27-28, 2021? Stop by
Interview with Shane Rau
We met recently with Shane Rau, Research Vice President at IDC, for a webinar to
Side-channel attacks explained: everything you need to know
In this blog post, we take an in-depth look at the world of side-channel attacks.
Advancing DDR5 RDIMMs to 5600 MT/s
Even as the industry ramps up for the initial launch of DDR5-based servers, it’s already
CXL Controller with Zero Latency IDE: You Can’t Do Better Than Zero
The virtuous cycle of data holds that as volume increases, the value increases. More volume
PCIe 5.0 Controller IP on FPGAs: Current and Future Use Cases
Rambus announced this week that it demonstrated for the first time a PCI Express 5.0
Rambus True Random Number Generator Certified to NIST SP 800-90B Standard
Cryptography depends on entropy. More specifically, every cryptographic protocol requires a source of non-deterministic (random)
Rambus Design Summit Featured Speaker: Steven Woo
Another week, another Rambus Design Summit wrap up! Over the coming weeks, we will be
Delivering Terabyte-Scale Bandwidth with HBM3-Ready Memory Subsystem
An exponential rise in data volume, and the meteoric rise of advanced workloads like AI/ML
Rambus Design Summit Featured Speaker: Frank Ferro
Thanks to everyone who joined us for Rambus Design Summit 2021. Over the coming weeks
451 Research Report: Interconnecting AnalogX and PLDA with Rambus
Compute Express Link (CXL) will enable memory expansion and pooling. Memory pooling with CXL 2.0
HBM2E data rate: Now up to 4 Gbps (20% Increase)
Joseph Rodriguez, senior product marketing engineer for IP cores at Rambus, has written an article
Automotive Security: Protecting vehicle electronic systems
Thierry Kouthon, a technical product manager at Rambus, recently wrote an article for Semiconductor Engineering
PLDA and AnalogX Acquisitions Supercharge the Rambus CXL Memory Interconnect Initiative
Big changes are coming to the data center driven by an exponential rise in data
New interface architectures enable data scaling
Suresh Andani, senior director of product marketing at Rambus, has written an article for Semiconductor
Anti-tamper protection: How to meet evolving threats
Scott Best, Technical Director of Anti-Counterfeiting Products at Rambus, recently penned an article for Semiconductor
Designing chiplet and co-packaged optics architectures with 112G XSR SerDes
Suresh Andani, senior director of product marketing at Rambus, has written an article for Semiconductor
Stacking memory for AI/ML training with HBM2E
Frank Ferro, Senior Director Product Management at Rambus, recently penned an article for Semiconductor Engineering
Powering the Next Wave of AI Applications
Artificial Intelligence/Machine Learning (AI/ML) grows at a blistering pace. The size of the largest training
Overcoming high-speed SerDes IP integration challenges: Part 2
In this two-part blog series based on a recent Semiconductor Engineering article, Rambus engineers Niall