Rambus Blog
The Security Risks of Silicon Complexity
Ben Levine, Senior Director of Security Product Marketing at Rambus, recently spoke with Semiconductor Engineering editor-in-chief Ed Sperling about the
Most Complex Processor Chip for AI Acceleration
EE Times reports that Graphcore of Bristol, UK has put on the market a new type of processor for AI acceleration.
Ben Levine Writes About CMRT Benefits in Embedded Computing Design Magazine
Ben Levine, Sr. Director, Product Marketing, Cryptography Products Division, recently penned an article in Embedded Computing Design Magazine letting SoC
Tech Firms Lax On Embedded Security
The glaring headline in a ComputerWeekly.com post is that “Nearly a quarter of tech firms do not security check their
How not to get pwned @ automotive cyber-security
Hacking a Tesla The past few weeks have been a busy time for white hat hackers demonstrating cyber-security vulnerabilities in
Rambus’ Ben Levine talks IoT security and cryptography with EDA Café
Ben Levine, Senior Director of Product Marketing at Rambus, recently sat down with Sanjay Gangal of EDA Café to discuss
Chipmakers: In the Horns of a Dilemma
Not since the inventions of the silicon transistor and integrated circuit (IC) have chipmakers found themselves in a quandary like
Is Post-Quantum Cryptography Necessary?
The burning question in some security scientists’ minds these days is: “Will post-quantum cryptographic algorithms be necessary in the future?”
Training Neural Networks
by Steven Woo Neural networks (NNs) span a wide range of topologies and sizes. Some neural networks are relatively simple
Rambus 112G SerDes PHY Article in eeweb.com/EE Times
Ken Dyer, Director, Engineering Architecture, is the author of a 112G Long Reach (LR) SerDes PHY article in eeweb.com/EE Times
112G LR SerDes PHY Ready for Next-Gen Networking Gear
Rambus has officially announced the 112G Long Reach (LR) SerDes PHY. Hemant Dhulla, VP and GM of IP Cores, said, “By
Digital Trends highlights Rambus CryptoManager Root of Trust
Jon Martindale of Digital Trends recently sat down with Ben Levine, Rambus’ senior director of product management, to discuss the
Fault Injection Attacks PlayStation Vita’s SoC
Security researcher Yifan Lu recently published a detailed paper that examines how voltage glitching causes critical timing violations in CMOS
Fault Injection Attacks: Bart Stevens Explains In eeweb.com/EE Times Article
We’ve all heard about micro-architectural vulnerabilities, Meltdown, Spectre, and Foreshadow. Volumes have been written about them in the trade and
Do You Know Your CVEs?
Do you know what CVEs are? Unless you’re linked up with security or cryptographic groupies, you probably don’t. Virtually everyone
From Multilayer Perceptrons to GANs
Written by Steven Woo In our previous blog post, we discussed the history of neural networks (NNs) and machine learning
Reduced-Precision Computation for Neural Network Training
In our previous blog post, we discussed the process of training neural networks (NN) and briefly touched on NN training
Understanding ML and ANN memory requirements
Written by Steven Woo Artificial Neural Networks First proposed in 1944 by Warren McCullough and Walter Pitts, an artificial neural
Paul Kocher Awarded 2019 Marconi Prize
Every year, The Marconi Society recognizes those individuals who have made a significant contribution to the advancement of communications for
GDDR6 Crosstalk Article – Rambus
Director of Signal Integrity Engineering at Rambus, Shawn Nikoukary, recently published a piece in eeweb.com/EE Times about crosstalk (xtalk) as
EE Times Article Series Touts RISC-V
Rich Quinnell, veteran semiconductor industry reporter, has written an EE Times article with the headline, RISC-V on the Verge of