Rambus Blog
Reassessing the HPC Memory Hierarchy
Written by Steven Woo As we’ve discussed in previous Rambus blog posts, high-performance computing (HPC) memory bandwidth and capacity are
An Introduction to HPC computing
Written by Steven Woo Dominated by the United States, Japan and China, the high-performance computing (HPC) space is driven by
Silex malware bricks unprotected IoT devices
Earlier this summer, a new strain of destructive malware known as Silex began to spread and effectively brick IoT devices.
Side-channel attack targets deep neural networks (DNNs)
All physical electronic systems routinely leak information about the internal process of computing via fluctuating levels of power consumption and
FIPS 140-3 and DPA: A Winning Combination
Recently, Rambus blogged about a large number of our DPARC and Crypto Accelerator Hardware Cores receiving FIPS-140-2 CAVP certification by
Selfblow exploits Tegra chipset vulnerability
A white hat researcher by the name of Triszka Balázs recently identified a security vulnerability that reportedly “affect[ed] every single”
Autonomous Vehicles: Memory Requirements & Deep Neural Net Limitations
Written by Steven Woo Introduction According to the National Highway Traffic Safety Administration (NHTSA), various driver assistance technologies are already
Taking the Show on the Road
Starting later this month, Rambus will host a series of lunch & learns around the globe entitled “Securing Electronic Systems
Let’s talk about neuromorphic computing
The term ‘neuromorphic computing’ can be traced back to the 1980s when Caltech researcher Carver Mead first proposed the concept
Securing the Infrastructure with the Global Semiconductor Alliance
By Paul Karazuba, Senior Director of Product Marketing, Cryptography Security, as always, was a hot topic at the recent Global
When a Chip Just Isn’t a Chip
When most people imagine counterfeit goods, they tend to picture the ‘Rolax’ watch that you can buy from that somewhat
Optimizing Non-Volatile Memory with NOVA and Ziggurat
Maximizing Hybrid Memory Systems with NOVA NOVA – a file system designed to maximize performance on hybrid memory systems –
Validating Cryptographic Algorithms to FIPS 140-2
NIST, the National Institute of Standards and Technology, is a United States Department of Commerce agency tasked with both the
Presenting Multiple Roots of Trust Across the World
Our friends at SiFive have been hosting a worldwide series of technical seminars, and Rambus has joined them for a
DPAWS 9.0: Easy Point and Click For Test and Security Engineers
It used to be that identifying and addressing potential side channel attack risks in semiconductor devices like SoCs was a
AI/ML ramps up despite training challenges
Training AI/ML algorithms A new survey commissioned by Alegion reveals that 8 out of 10 companies have found training AI/ML
Are ML Systems Robust Enough for the Here and Now?
Researchers at MIT have created a way to determine robustness levels of machine learning (ML) models for various tasks. And
Will Neuromorphic Chips Outpace AI Processors?
Add this one to your list of artificial intelligence (AI) terms — neuromorphic chips. They’re described as chips that model
The Autobahn Lanes of HBM2 and GDDR6
Narrow roads versus silicon superhighways Steven Woo, Rambus fellow and distinguished inventor, recently spoke with Ed Sperling of Semiconductor Engineering
What About AI Regulations?
These days, there’s considerable talk and hoopla surrounding artificial intelligence/AI. Tech companies on a worldwide basis are talking about how
The Security Risks of Silicon Complexity: Part 2
In part one of this two-part blog series, Ben Levine, Senior Director of Security Product Marketing at Rambus, and Semiconductor