Written by Frank Ferro and Lou Ternullo
We wrapped up a great PCI-SIG Developers Conference (DevCon) last week which really showed off the strength and momentum of the PCI Express® community. There was great engagement with everyone who stopped by the booth, and we appreciate the time of everyone who had the chance to do so. While PCIe 5.0 just recently reached the market in the latest state-of-the-art server and client systems, the demand for more bandwidth is unrelenting. So, this DevCon was the opportunity to shine the spotlight on the generation for the next wave of computing systems: PCIe® 6.0.
PCIe 6.0 represents a real watershed event for the standard, because for the first time in its storied history, we’re moving from tried-and-true NRZ to a new signaling scheme, PAM4. With PAM4 signaling (“Pulse Amplitude Modulation with four levels”) you get 2 bits per clock cycle for 4 amplitude levels (00, 01, 10, 11) vs. PCIe 5.0, and earlier generations, which used NRZ modulation with 1 bit per clock cycle and two amplitude levels (0, 1). With PAM4, instead of talking about a clean eye, we need to talk about “three clean eyes” between the four voltage levels.
That’s exactly what we demo’ed at DevCon, with our PCIe 6.0 PHY running at 64 GT/s. In long reach and short reach implementations, we showed off Bit Error Rate (BER) performance that far exceeded the spec. With SI/PI being integral to our engineering DNA, we’ve designed our PHY with the headroom to ensure first-time right implementations for the most demanding applications.
Given PAM4’s inherently higher BER compared to NRZ, the PCIe 6.0 standard incorporates Forward Error Correction (FEC) in the controller to mitigate the higher error rate. The PCIe 6.0 FEC is kept lightweight to have minimal impact on latency (under 2ns). FECs required fixed sized packets, so away go the variable packets of PCIe 5.0 and in come FLITs with PCIe 6.0.
FLIT mode packets are organized in Flow Control Units of fixed sizes, as opposed to variable sizes of past PCIe generations. In addition to supporting FEC, FLIT mode also simplifies data management at the controller level and results in higher bandwidth efficiency, lower latency, and smaller controller footprint.
In our PCIe 6.0 Digital Controller demo we showed operation to the full PCIe 6.0 spec. including FLIT mode. We sent Transaction Layer Packets (TLP) both from Root Port to Endpoint, and Endpoint to Root Port. This demo used Root Port and End Point instantiations of the Rambus PCIe 6.0 Controller IP implemented into two internally developed FPGA boards to accommodate the current unavailability of PCIe 6.0 Host devices. We utilized our internally developed embedded debugger and logic analyzer, XpressAGENT, to trace and display TL Packets. In compliance with the PCIe 6.0 specification, the controller is backwards compatible to non-FLIT mode NRZ operation when interoperating with PCIe 5.0 and earlier generation devices.
Whether you need a PCIe 6.0 PHY, PCIe 6.0 Digital Controller or a full PCIe 6.0 Interface Subsystem, we’ve got you covered. You can check out all our PCIe IP offerings here and get in touch with us at rambus.com.