Get Ready for DDR5 DIMM Chipsets
This entry was posted on Thursday, January 31st, 2019.
Doug Daniels, Senior Manager, Applications Engineering at Rambus, recently penned an article for eeweb.com/EE Times, giving server/system designers a heads up on what to expect when transitioning from DDR4 to DDR5 server dual-in line memory module (DIMM) buffer chipsets in their upcoming designs.
The DDR4 buffer chip generation is faring well in the market according to industry experts. But the new generation of DDR5 buffer chips are at the doorstep knocking and ready to move in to help further advance server performance.
Daniels says server and system design engineers can expect a bevy of new specification changes involved in the transition from DDR4 to DDR5. The top six he describes in his article are data and clock rate, VDD or operating voltage, power architecture, channel architecture, burst length, and improvements for higher-capacity DRAM support.
DDR4 date rate is 3200 megatransfers per second (MT/s) at 1.6 gigahertz (GHs) clock rate. Better hold on to your hat because DDR5 starts at that 3200 MT/s at the low end and swiftly move towards data rates of 6400 MT/s and clock rates of 3.2 GHz. Not only that, but there’s talk in the industry about higher speeds than that. Greater speeds mean higher performance, but the tradeoff for server and system designers they also mean major design challenges.
The second major change that’s expected is VDD or operating voltage.Here DRAM and buffer chip registering clock driver (RCD) drops from 1.2 volts down to 1.1 volt. This saves power, but it’ll also add some challenges to DIMM designs.
Power architecture is expected to be another major change, according to Daniels. DIMMs will have a 12- volt power management IC (PMIC) on them. This permits better granularity on the system’s power loading. This PMIC that drops out to the 1.1- volt supply also helps with signal integrity and noise because designers will have better on-DIMM control of the power supply.
A most notable change for DDR5 is a new DIMM channel architectureDDR4 buffer chip DIMMs have a 72-bit bus, comprised of 64 data bits plus eight ECC bits. With DDR5, each DIMM will have two channels. However, they’ll be 32 bits plus eight ECC bits each, thus two 40-bit channels compared to one 72-bit data channel.
This helps gain efficiency. It also makes the DIMM design more symmetrical because the left and right side of the DIMM coming from each channel share the RCD. So, now, there’ll be five 8-bit lanes at each channel for each side of the RCD. Hence, there are two DIMM channels with only one RCD, and it’ll have two sets of outputs, the A and B side.
Other features are added for improvements with that channel architecture. In DDR4, there are two output clocks from the RCD for each side of the DIMM. In DDR5, there’ll be four output clocks per side. This gives each lane an independent clock, which helps with signal integrity for the clock signal.
The fifth major change is burst length. DDR4 burst length is eight and burst chop length is four. For DDR5, burst length and burst chop will be extended to increase burst payload, even with the narrower channel (32 bits vs. 64 bits). Since there will be two channels per DIMM with equal or greater burst payload, memory efficiency will be increased.
A sixth change for DDR5 will be improvements for higher capacity DRAM support. With DDR5 buffer chip DIMMs, the server or system designer can go up to 32 Gb DRAMs in a single die package. DDR4 is currently maxing out at 16 Gb in a single die package. DDR5 will support features like on-die ECC, error transparency mode, post-package repair and read and write CRC modes to support higher capacity DRAMs.