Memory Interface Chips
Server DIMM Chipsets
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Solution Overview| Products | Part Number | Data Rate |
|---|---|---|
| DDR5 DIMM Chipset | ||
| DDR4 Non-volatile Register Clock Driver | iDDR4NVRCD2 | 1600/1866/2133/2400/2666/2933/3200 |
| DDR4 Register Clock Driver | iDDR4RCD-GS02 | 2400/2666 |
| DDR4 Data Buffer | iDDR4DB2-GS02 | 2400/2666 |
| DDR3 Register Clock Driver | INSSTE32882XV | 1600/1866/2133 |
| DDR3 Isolation Memory Buffer | iMB02-GS02B | 1600/1866 |
Superior Performance
Fully compliant with the latest JEDEC performance specifications for DDR4 2400 Mbps
Operational up to 2666 Mbps
Enhanced Margin
Wide margin I/O design with advanced programmability
Exceeds JEDEC reliability standards for ESD and EOS
Optimized Power
Advanced power management
Frequency-based, low-power optimization
Best-in-class Debug
Integrated tools for bring-up and debug
Works out-of-the-box with default BIOS
RDIMM, LRDIMM & NVDIMM Chipsets
Our DDR3 and DDR4 chipsets, recently acquired from Inphi, for RDIMM and LRDIMM enable top-of-the-line performance and capacity with optimized power efficiency to advance critical data center and enterprise server infrastructure for the growing demands of big data. Our DDR4 non-volatile register clock driver enables NVDIMM-N persistent memory products and paves the way emerging NVDIMM-P architectures.
Our chipsets feature industry-leading I/O performance and margin, running up to 2666 Mbps and leveraging advanced power management techniques to meet stringent thermal requirements and reduce cost of ownership. The server DIMM chipsets enable a wide array of memory-intensive applications, including real-time analytics, in-memory computing, virtualization and business intelligence.
The chipsets simplify cross-platform SKU management with a wide operating range and works with the default system BIOS to ease integration. Combined with best-in-class debug and support capabilities, the DDR memory chipsets for RDIMM, LRDIMM and NVDIMM ensure rapid integration, faster time-to-market and robust system operation.
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