Enabling faster cryptographic processing in SoC devices, Rambus cryptographic algorithm IP cores accelerate symmetric and asymmetric ciphers, and Hash- and HMAC-based integrity algorithms. DPA resistance provides robust protection from side channel attacks.
Crypto accelerator cores offer chipmakers an easy-to-integrate technology-independent soft-macro security solution, offering various levels of cryptographic acceleration performance.
They are easy to integrate into various SoC and FPGA architectures and development flows. The cores are designed to maximize performance versus silicon area requirements. These cores pass all NIST CAVP vectors. Differential Power Analysis (DPA) protected versions have been extensively validated using the standardized Test Vector Leakage Assessment (TVLA) methodology.
The crypto accelerator cores are provided as RTL reference designs, allowing customers to target their CMOS node or FPGA family of choice. The cores can be integrated into any architecture, e.g. with an appropriate wrapper as bus attachments on an SoC bus, or as part of an inline streaming crypto pipeline. The design data base comprises of a testbench, test vectors, integration data, simulation and synthesis scripts, that can all be adapted easily to match a preferred design flow and tool chains.
Side-channel attacks conducted against electronic gear are relatively simple and inexpensive to execute. Such attacks include simple power analysis (SPA) and Differential Power Analysis (DPA). As all physical electronic systems routinely leak information, effective side-channel countermeasures should be implemented at the design stage to ensure protection of sensitive keys and data.
Don’t miss out on the Rambus Design Summit on October 8th!