AES-IP-36 AES ECB/CBC/CTR accelerators

The AES-IP-36 (EIP-36) is IP for accelerating the AES symmetric cipher algorithm (FIPS-197), supporting ECB, CBC and CTR modes up to 12.8 Gbps @ 1GHz. Designed for fast integration, low gate count and full transforms, the AES-IP-36 accelerator provides a reliable and cost-effective embedded IP solution that is easy to integrate into high speed crypto pipelines.

AES family of accelerators.

Available in six configurations / performance grades.

Library element for security packet engines.

How the AES-IP-36 AES ECB/CBC/CTR Accelerators work

The AES-IP-36 is a family of the cryptographic library elements in the Rambus hardware IP library (formerly of Inside Secure). For example, the AES-IP-36 is the cipher core embedded in all PacketEngine-IP-97/196/197 protocol-aware security engines. The accelerators include I/O registers, encryption and decryption cores, and the logic for feedback modes and key scheduling.

Sustained performance for any object sizes ranges from 2.5 to 12.8 Gbps depending on the configuration and area. Gate count is between 23K and 52K gates depending on the configuration. Multiple AES-IP-36 cores can be cascaded.

Rambus also offers the AES-IP-39 that supports more AES modes and can be provided with counter measures including ones against side-channel attacks and fault injection attacks.

AES-IP-36 AES ECB/CBC/CTR Accelerators
AES-IP-36 AES ECB/CBC/CTR Accelerators
Watch Anti-Tampering Technologies Webinar

Anti-Tampering Technologies

The design of chip anti-tamper protection needs to adapt and scale with rising threats. Adversaries range from high school hackers to well-funded state actors. Given the threats, it’s useful to think about anti-tamper countermeasures as a hierarchy of safeguards that parallel the type, effort and expense of attacks. Watch this webinar to learn the eleven kinds of tampering attacks and their required skills and resources, and countermeasures for each of these attacks.

AES-IP-36 Information

Key benefits:

  • Silicon-proven implementation
  • Fast and easy to integrate into SoCs
  • Flexible layered design
  • Complete range of configurations
  • World-class technical support


  • Wide bus interface (128-bit data, 256-bit keys) or 32-bit register interface
  • Key sizes: 128, 192 and 256 bits
  • Includes key scheduling hardware
  • Feedback modes: ECB, CBC, CTR, OFB (128 bit), 
CFB (1, 8 and 128 bit)
  • Fully synchronous design
  • Low Speed, Medium Speed, High Speed versions
  • Encrypt-only versions (aimed at Counter Mode) for 
each speed version


  • AES-IP-32 AES ECB accelerators
  • AES-IP-36 AES ECB/CBC/CTR accelerators
  • AES-IP-37 AES Key Wrap accelerators
  • AES-IP-38 AES XTS/GCM accelerators
  • AES-IP-39 AES ECB/CBC/CTR/CCM/GCM accelerators
Introduction to Side-Channel Attacks eBook

Introduction to Side-Channel Attacks

Side-channel attacks conducted against electronic gear are relatively simple and inexpensive to execute. Such attacks include simple power analysis (SPA) and Differential Power Analysis (DPA). As all physical electronic systems routinely leak information, effective side-channel countermeasures should be implemented at the design stage to ensure protection of sensitive keys and data.

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