Security division Icon

Security

DPA Resistant Core

Addressing the growing demand for readily available solutions that implement Differential Power Analysis (DPA) countermeasures, we developed a family of cryptographic cores and software libraries that are designed to protect against side-channel attacks. Our DPA Resistant cores are validated to resist first– and second– order DPA attacks up to 10 million traces and can be optimized for size, speed and security level.

Contact

Product Brief

DPA Resistant Core block diagram

How it works

The DPA Resistant AES Core is a high-security AES primitive that offers chipmakers an easy-to-integrate security solution with built-in side-channel resistance for cryptographic functions across a wide range of devices.

Easy-to-integrate into SoCs and FPGAs, this high-performance core provides a higher level of protection than standard AES cores. It is highly flexible for integration with standard cipher modes such as Cipher Block Chaining (CBC), Electronic Code Book (ECB), etc.

This high-performance core offers both encryption and decryption functions with key size options of 128- and 256-bits.

It implements DPA countermeasures such as LMDPL (LUT-Masked Dual-rail with Pre-charge Logic) gate level masking and other schemes, to deliver the highest level of security. These countermeasures are portable to any FPGA and ASIC technologies

Solution Offerings

Inventions

DPA Countermeasures

security-icon

DPA Countermeasures are fundamental techniques for protecting against Differential Power Analysis (DPA) and related side-channel attacks. Consisting of a broad range of software, hardware, and protocol techniques, DPA Countermeasures include reducing leakage, introducing amplitude and temporal noise, balancing hardware and software, incorporating randomness, and implementing protocol level countermeasures.

From the blog

Related Markets & Applications

IoT