AES-IP-39 AES “All Modes” Accelerators

The AES-IP-39 (EIP-39) is IP for accelerating the AES symmetric cipher algorithm (FIPS-197), supporting all NIST modes including ECB, CBC, CTR, CFB, OFB, CCM, GCM, CBC-MAC, CMAC, XTS, F8, F9 modes of operation up to 6.4 Gbps @ 1GHz. Designed for fast integration, low gate count and full transforms, the AES-IP-39 accelerator provides a reliable and cost-effective embedded IP solution that is easy to integrate into security modules needing versatile crypto.

AES family of accelerators, all modes.

Optional counter measures against side channel attacks and fault injection attacks.

Library element for VaultIP platform security engine.

How the AES-IP-39 AES “All Modes” Accelerators work

The AES-IP-39 is a family of the cryptographic library elements in the Rambus hardware IP library (formerly of Inside Secure). For example, the lightweight configuration of the AES-IP-39 is the cipher core embedded in all Vault-IP platform security engines as well as the Crypto-IP-120 DMA crypto core. The accelerators include I/O registers, encryption and decryption cores, and the logic for feedback modes and key scheduling.

AES-IP-39 "all modes" accelerator
AES-IP-39 "all modes" accelerator

Sustained performance for any object sizes ranges from 1 to 6.4 Gbps depending on the configuration and area. Gate count is between 27K and 45K gates depending on the configuration.

The AES-IP-39 can be provided with counter measures including ones against side-channel attacks and fault injection attacks.

Watch Anti-Tampering Technologies Webinar

Anti-Tampering Technologies

The design of chip anti-tamper protection needs to adapt and scale with rising threats. Adversaries range from high school hackers to well-funded state actors. Given the threats, it’s useful to think about anti-tamper countermeasures as a hierarchy of safeguards that parallel the type, effort and expense of attacks. Watch this webinar to learn the eleven kinds of tampering attacks and their required skills and resources, and countermeasures for each of these attacks.

AES-IP-39 Information

Key benefits:

  • Silicon-proven implementation
  • Fast and easy to integrate into SoCs
  • Flexible layered design
  • Complete range of configurations
  • World-class technical support


  • 32-bit register interface
  • Key sizes: 128, 192 and 256 bits
  • Includes key scheduling hardware
  • Feedback modes: ECB, CBC, CTR, OFB-128, 
  • Protocol modes: CCM, GCM, CMAC and XCBC-MAC
  • Optional modes: AES-XTS, OFB, f8 and f9
  • Fully synchronous design
  • Low Speed, Medium Speed, High Speed versions
  • Optional counter measures against side channel attacks and fault injection attacks
  • Standard Compliance: FIPS-197, NIST-SP800-38A/B/C/D/E


  • AES-IP-32 AES ECB accelerators
  • AES-IP-36 AES ECB/CBC/CTR accelerators
  • AES-IP-37 AES Key Wrap accelerators
  • AES-IP-38 AES XTS/GCM accelerators
  • AES-IP-39 AES ECB/CBC/CTR/CCM/GCM accelerators
Introduction to Side-Channel Attacks eBook

Introduction to Side-Channel Attacks

Side-channel attacks conducted against electronic gear are relatively simple and inexpensive to execute. Such attacks include simple power analysis (SPA) and Differential Power Analysis (DPA). As all physical electronic systems routinely leak information, effective side-channel countermeasures should be implemented at the design stage to ensure protection of sensitive keys and data.

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