Focused on advancing single-ended signaling technologies to meet the memory system requirements of next-generation computing applications while maintaining compatibility with current industry standard DDR4 solutions, this next-generation R+ main memory architecture advances single-ended signaling up to 6.4 gigabits per second (Gbps) in a multi-rank, multi-DIMM system.
Demand for an enriched end-user experience and increased performance in next-generation mainstream computing applications is unremitting. Driven by multi-core computing, virtualization and processor integration trends, the industry needs a next-generation main memory solution capable of achieving data rates of up to 6400Mbps in the same, or lower power envelope as current DDR4 memory solutions. The divergence of these two requirements, increasing performance while lowering power, presents a difficult challenge for future memory system designers.
In addition, next-generation memory solutions face potential bottlenecks in access efficiency and capacity, both of which have fallen as date rates increased. Memory module upgrades are the most common way to increase capacity in a system. The number of modules supported on a DDR4 memory channel drops at high data rates due to degraded signal integrity. This problem has led to a change in topology from multiple DIMMs per memory channel to a point-to-point topology that only supports a single DIMM per memory channel. This makes a DDR4 memory system difficult to scale and non-ideal for most server, workstation and high-end PCs. Memory access granularity also suffers as data rates increase due to the disparity between the interface and core access speeds. The result is an increase to the core prefetch and a sub-optimal transfer size for future multi-core and graphics computing applications.
The R+ technologies for extending main memory address these issues by enabling single-ended signaling to go beyond DDR4 in a power-efficient and cost-effective manner.
Near Ground Signaling
Near Ground Signaling (NGS) is a single-ended, ground-terminated signaling technology that enables high data rates at significantly reduced Input Output (IO) signaling power and design complexity, while maintaining excellent signal integrity. This allows devices to achieve higher data rates with significantly reduced IO power.
Module Threading improves the throughput and power efficiency of a memory module by applying parallelism to module data accesses, ensuring high sustained and peak bandwidth for future multi-core CPUs. Minimum transfer size and row activation power are reduced by partitioning the module into two individual memory channels with interleaved commands.
DPP technology maintains the signal integrity benefits of point-to-point signaling on the data bus while providing the flexibility of capacity expansions with module upgrades. Memory modules can be dynamically reconfigured to support different data bus widths, allowing a memory controller with a fixed data bus width to connect to a variable number of modules.