At Rambus, we create cutting-edge semiconductor and IP products, providing industry-leading chips and silicon IP to make data faster and safer.
Found 3610 Results
UET-TSS-IP-69 Product Brief
https://go.rambus.com/uet-tss-ip-69-product-brief#new_tabThe UET-TSS-IP-69 is a multi-channel Ultra Ethernet TSS transformation engine providing full line-rate throughput up to 1.6T. It supports all UET-TSS features.
UET-TSS-IP-369 Product Brief
https://go.rambus.com/uet-tss-ip-369-product-brief#new_tabDownload this product brief to learn about the Rambus UET-TSS-IP-369, a multi-channel Ultra Ethernet TSS complete layer solution with rates up to 1.6T.
Rambus Announces Industry-Leading Ultra Ethernet Security IP Solutions for AI and HPC
https://www.rambus.com/blogs/rambus-announces-industry-leading-ultra-ethernet-security-ip-solutions-for-ai-and-hpc/AI/HPC clusters process a tremendous volume of valuable data and have already become a critical element of modern infrastructure and therefore must be protected at all levels that are exposed to potential threats. Network security is one of the key components aiming to provide: Access control – allowing only the authorized nodes or users to […]
Multi-channel Ultra Ethernet TSS Transform Engine (UET-TSS-IP-69)
https://www.rambus.com/security/protocol-engines/uet-tss-ip-69/The UET-TSS-IP-69 (EIP-69) is a high-performance, multi-channel transform engine that provides the complete TSS packet transformation (including KDF and IP/UDP updates), bypass/drop and basic crypto processing at rates up to 1.6Tbps. The engine is designed for integration into the systems that require TSS processing for one or more ports. The engine is provided as separate ingress and egress data paths.
Multi-channel Ultra Ethernet TSS Complete Layer (UET-TSS-IP-369)
https://www.rambus.com/security/protocol-engines/uet-tss-ip-369/The UET-TSS-IP-369 (EIP-369) is an inline, high-performance, multi-channel packet engine that provides the complete TSS layer, bypass/drop and basic crypto processing at rates up to 1.6Tbps.
ZQ Calibration
https://www.rambus.com/chip-interface-ip-glossary/zq-calibration/ZQ Calibration is a process used in DDR (Double Data Rate) SDRAM memory systems—such as DDR3, DDR4, and DDR5—to precisely adjust the on-die termination (ODT) and output driver impedance of the DRAM.
VDC-M (Voltage Droop Control – Memory)
https://www.rambus.com/chip-interface-ip-glossary/voltage-droop-control-memory/VDC-M (Voltage Droop Control for Memory) is a power integrity feature implemented in high-speed memory systems, such as DDR5 and LPDDR5, to detect and mitigate voltage droop events that can compromise data reliability.
TLP (Transaction Layer Packet)
https://www.rambus.com/chip-interface-ip-glossary/transaction-layer-packet/A Transaction Layer Packet (TLP) is the fundamental unit of communication in the PCI Express (PCIe) protocol, used to encapsulate data and control information exchanged between devices. TLPs are generated and processed at the Transaction Layer of the PCIe stack and are responsible for carrying out all high-level PCIe operations, including memory reads/writes, I/O transactions, and configuration accesses.
SoC (System on Chip)
https://www.rambus.com/chip-interface-ip-glossary/system-on-chip/A System on Chip (SoC) is an integrated circuit that consolidates all essential components of a computer or electronic system, including CPU, GPU, memory controllers, I/O interfaces, and often specialized accelerators, onto a single chip
Signal Regeneration
https://www.rambus.com/chip-interface-ip-glossary/signal-regeneration/Signal regeneration is the process of restoring degraded or attenuated electrical or optical signals to their original quality during transmission across long distances or through high-speed interconnects. It is essential in high-speed communication systems, such as PCIe, Ethernet, and optical networks, where signal integrity deteriorates due to noise, dispersion, or loss over cables, backplanes, or fiber.
