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Read this blog to learn how DDR5 DIMM chipsets work, why they matter, how they build upon DDR5 technology, and how emerging module architectures such as MRDIMMs are extending memory bandwidth for demanding AI and data center workloads.
[Aug 18 at 11am PT] Join Rambus for a live webinar as we explore the industry’s transition from traditional aggregated servers to modern scale-up, scale-out, and disaggregated architectures. We will also discuss the critical role of PCI Express® (PCIe®) as the foundational interconnect for next-generation infrastructure and explains how PCIe switches and PCIe retimers enable […]
As artificial intelligence workloads evolve from model training to real-time inference and autonomous agentic workflows, the demands placed on system memory continue to rise rapidly. The modern data center is constrained not only by compute, increasingly it is defined by memory bandwidth, memory capacity, and power efficiency. To address these challenges, Rambus is introducing the […]
The Rambus Registering Clock Driver (RCD) RCD06 enables DDR5 Registered DIMMs (RDIMMs) operating up to 9600 MT/s. Download this brief to review the RCD functional block diagram, see the specifications and features, and check out the DDR5 RDIMM block diagram.
SAN JOSE, Calif. – July 8, 2026 – Rambus Inc. (NASDAQ: RMBS), a premier chip and silicon IP provider making data faster and safer, today announced its DDR5 9600 Server RDIMM chipset designed to deliver industry-leading memory performance for next-generation data center platforms. Built around the new Rambus 6th Generation Registering Clock Driver (RCD06) with a 20% increase in bandwidth over the prior generation, this complete chipset enables RDIMMs operating at up to 9600 MT/s, unlocking a new level of bandwidth and capacity required by agentic AI, high-performance computing (HPC) and other data-intensive workloads.
Download this white paper to explore how DDR5 DIMMs address these emerging requirements, delivering significant advancements in data rate, density, power efficiency, and channel architecture over DDR4. It examines the role of DDR5 as the foundational memory layer in modern AI infrastructure, complementing heterogeneous compute architectures and supporting highly concurrent, data-driven workloads, while also outlining […]
Watch the video to learn how PCIe 7 switching enables efficient communication between GPUs, SmartNICs, SuperNICs, storage, and memory resources in large-scale AI deployments.
The transition to post-quantum cryptography (PQC) has moved from research planning to operational execution. Federal policy, emerging procurement requirements, and evolving security standards are accelerating the adoption of quantum resistant cryptography across government and critical infrastructure systems. Recent U.S. government actions, including Executive Order 14409, are accelerating the shift to quantum-resistant cryptography across federal systems […]
As the automotive industry transitions to software-defined vehicles (SDVs), security architectures must evolve from discrete features into integrated, platform-level capabilities. The next generation of automotive SoCs requires not only stronger security, but a more standardized and extensible foundation that aligns with broader silicon ecosystems. Rambus is addressing this need with the introduction of the automotive-grade […]
Download this brief to review the Rambus RT-648 Embedded HSM Root of Trust with Arm Cortex-M33 Processor.
