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SAN JOSE, Calif. – February 12, 2026 – Rambus Inc. (NASDAQ: RMBS), a premier chip and silicon IP provider making data faster and safer, today announced the appointment of Victor Peng to its Board of Directors, effective Thursday, February 12, 2026. Mr. Peng is an accomplished executive with more than 40 years of leadership experience […]
John Allen Vice President & Chief Accounting Officer John Allen is vice president and chief accounting officer at Rambus. John joined the company in 2023 and leads the global accounting organization with over 40 years of finance experience. Before joining Rambus, John served as senior vice president and corporate controller at Xperi (formerly Tessera), including […]
SAN JOSE, Calif. – February 10, 2026 – Rambus Inc. (NASDAQ: RMBS), a premier chip and silicon IP provider making data faster and safer, today announced that Desmond Lynch, senior vice president and chief financial officer (CFO), will resign from Rambus effective February 27, 2026, to pursue another opportunity. A formal search has commenced for […]
Dr. Simon Blake-Wilson joined Rambus in January 2026 and currently serves as the Senior Vice President and General Manager of Silicon IP at Rambus. He is responsible for the development and growth of the company’s silicon IP products, driving high-performance, secured memory and interconnect architectural innovation in Data Center and Edge Connectivity applications.
As artificial intelligence (AI) continues to proliferate across industries – from smart cities and autonomous vehicles to industrial automation, robotics, edge servers, and consumer electronics – edge inferencing has become a cornerstone of next-generation computing.
SDRAM is a type of dynamic random access memory (DRAM) that synchronizes its operations with the system bus clock, allowing for predictable and high-speed data access.
Register Transfer Level (RTL) is a design abstraction used in digital circuit design that describes the flow of data between hardware registers and the logical operations performed on that data.
In PCI Express (PCIe) architecture, a Root Port is a type of port located in the Root Complex, which connects the CPU and memory subsystem to PCIe devices. It initiates PCIe transactions and manages communication between the host system and downstream components such as endpoints, switches, and bridges.
Reorder Functionality refers to the capability within high-speed data transmission systems, such as memory controllers, interconnect protocols (e.g., PCIe, CXL), and network-on-chip (NoC) architectures, to restore the correct sequence of data packets or memory transactions that arrive out of order.
Reed-Solomon (RS) is a powerful error correction code (ECC) used to detect and correct multiple symbol errors in digital data transmissions and storage.
