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As AI workloads reshape modern data centers, memory is one of the most critical factors for performance, efficiency, and total cost of ownership. While CPUs and accelerators continue to scale rapidly, AI server architectures are increasingly power‑limited and thermally constrained. This has driven growing interest in Low Power DDR (LPDDR) as a server memory technology. […]
Download this product brief to learn more about the Rambus 12 Amp Voltage Regulator for Server SOCAMM2.
Rambus Voltage Regulators for LPDDR5X-based SOCAMM2 enable a broad range of performance and capacity configurations for AI servers.
SAN JOSE, Calif. — Apr. 22, 2026 — Rambus Inc. (NASDAQ: RMBS), a premier chip and silicon IP provider making data faster and safer, today announced a SOCAMM2 (Small Outline Compression Attached Memory Module) chipset designed to enable low-power, high-performance LPDDR5X-based memory modules for AI server platforms.
Supporting low-power, high-performance memory modules for AI, the Rambus SOCAMM2 Server Chipset enables the operation of LPDDR5X-based SOCAMM2 modules.
At Rambus, we spend a lot of time solving hard problems at the intersection of memory and compute. Bandwidth limits. Power integrity. Signal integrity. Thermal constraints. These challenges become even more complex as AI training, inference, and high-performance computing push memory subsystems to their limits. That is why industry recognition matters less as a trophy […]
In this webinar, Rambus experts will explore how complete client memory interface chipsets enable high‑performance DDR5 CUDIMM and CSODIMM modules operating up to 7200 MT/s, with capabilities for overclocking. Also covered will be chipsets for the latest LPCAMM2 modules designed for thin, power‑efficient client systems. Attendees will gain insight into the architectural challenges of high‑speed […]
This webinar examines why reliability and security have become inseparable drivers for next‑generation automotive chips, and how a lifecycle‑based approach is required to meaningfully reduce recall risk. We will review real‑world examples of recalls caused by electronic failures, explore the evolving standards landscape driving higher expectations for reliability and traceability, and walk through the end‑to‑end chip lifecycle from wafer fabrication to in‑vehicle operation.
n this webinar, Rambus experts will explore how complete client memory interface chipsets enable high‑performance DDR5 CUDIMM and CSODIMM modules operating up to 7200 MT/s, with capabilities for overclocking. Also covered will be chipsets for the latest LPCAMM2 modules designed for thin, power‑efficient client systems. Attendees will gain insight into the architectural challenges of high‑speed client memory, including signal integrity, power delivery, sideband management, and thermal considerations, and how Rambus chipset solutions address these challenges at the module level.
MACsec (Media Access Control Security) is an Ethernet security standard that encrypts and authenticates data in motion at Layer 2 of the OSI model, protecting traffic as it moves between directly connected devices. In this blog, we’ll explore what MACsec is, how it works, how it compares to higher-layer security approaches, and why it is essential for modern Ethernet-based systems.
