Rambus

At Rambus, we create cutting-edge semiconductor and IP products, providing industry-leading chips and silicon IP to make data faster and safer.

Chip + Interface IP Glossary

A glossary of Chip and Interface IP terminology and relevant solutions.

A

Application-Specific Integrated Circuit (ASIC)
Advanced eXtensible Interface (AXI)

B

Bank Management
Bank Refresh

C

Clamshell Mode
Controller
Crosslink
Camera Serial Interface (CSI-2)

D

Data Bus Inversion
Design Failure Mode and Effects Analysis (DFMEA)
DisplayPort
Display Serial Interface (DSI)​
Display Stream Compression (DSC)
DMA Engine

E

Error Correction Code (ECC)
End-to-End CRC (ECRC)
End-to-End Data Parity
Endpoint Switch

F

Failure Modes, Effects, and Diagnostic Analysis (FMEDA)
Flow Control Unit (FLIT)
Forward Error Correction (FEC)

H

High-Performance Computing (HPC)

I

In-line ECC
Integrated Development Environment Security (IDE Security)
Integrated Reorder Functionality
Interconnect

L

Lane Management
Lane Operation
Look-ahead Activate, Precharge, and Auto Precharge Logic
Lossless Compression

M

Memory Test Analyzer
Message Signaled Interrupts (MSI)
Multi-Function
Multi-modal
Multi-Port Front-End

P

PAM3 and PAM4
Parity Protection
PHY Interface for PCI Express (PIPE)
Pixel to Byte Packing
Port Dual-Mode

N

Non-Return-to-Zero (NRZ)

R

Reliability, Availability, and Serviceability (RAS)
Read-Modify-Write (RMW)
Reed-Solomon (RS) Code
Reorder Functionality
Root Port
Register Transfer Level (RTL)

S

Synchronous Dynamic Random Access Memory (SDRAM)
Signal Regeneration
System on Chip (SoC)

T

Transaction Layer Packet (TLP)

V

Voltage Droop Control – Memory (VDC-M)

Z

ZQ Calibration

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